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riscv-formal-nmigen
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Update README.md

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Donald Sebastian Leung 2020-08-27 16:25:54 +08:00
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@ -102,12 +102,19 @@ Below is a list of instructions currently supported by this port of the riscv-fo
- `InsnSlliw`: SLLIW instruction
- `InsnSrliw`: SRLIW instruction
- `InsnSraiw`: SRAIW instruction
- `InsnRV64IRType`: RV64I R-Type Instruction
- `InsnAddw`: ADDW instruction
- `InsnSubw`: SUBW instruction
- `InsnSllw`: SLLW instruction
- `InsnSrlw`: SRLW instruction
- `InsnSraw`: SRAW instruction
- `InsnSd`: SD instruction
### ISAs
- `IsaRV32I`: RV32I Base ISA
- `IsaRV32M`: RV32M Standard Extension
- `IsaRV64I`: RV64I Base ISA
## Core-specific parameters