Refactor instructions to use NamedTuple

rvfi/insns/insn.py

@@ -1,45 +1,42 @@
 from nmigen import *
 
 """
-Insn.py
+General RISC-V Instruction
-Class for generic RISC-V instructions
 """
 
 class Insn(Elaboratable):
-    def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA):
+    def __init__(self, params):
-        # Core-specific constants
+        # Core-specific parameters
-        self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
+        self.params = params
-        self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
-        self.RISCV_FORMAL_CSR_MISA = RISCV_FORMAL_CSR_MISA
 
         # RVFI input ports
         self.rvfi_valid = Signal(1)
-        self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
+        self.rvfi_insn = Signal(self.params.ilen)
-        self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
+        self.rvfi_pc_rdata = Signal(self.params.xlen)
-        self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
+        self.rvfi_rs1_rdata = Signal(self.params.xlen)
-        self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
+        self.rvfi_rs2_rdata = Signal(self.params.xlen)
-        self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
+        self.rvfi_mem_rdata = Signal(self.params.xlen)
-        if self.RISCV_FORMAL_CSR_MISA:
+        if self.params.csr_misa:
-            self.rvfi_csr_misa_rdata = Signal(self.RISCV_FORMAL_XLEN)
+            self.rvfi_csr_misa_rdata = Signal(self.params.xlen)
 
         # RVFI output ports
-        if self.RISCV_FORMAL_CSR_MISA:
+        if self.params.csr_misa:
-            self.spec_csr_misa_rmask = Signal(self.RISCV_FORMAL_XLEN)
+            self.spec_csr_misa_rmask = Signal(self.params.xlen)
         self.spec_valid = Signal(1)
         self.spec_trap = Signal(1)
         self.spec_rs1_addr = Signal(5)
         self.spec_rs2_addr = Signal(5)
         self.spec_rd_addr = Signal(5)
-        self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
+        self.spec_rd_wdata = Signal(self.params.xlen)
-        self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
+        self.spec_pc_wdata = Signal(self.params.xlen)
-        self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
+        self.spec_mem_addr = Signal(self.params.xlen)
-        self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
+        self.spec_mem_rmask = Signal(int(self.params.xlen // 8))
-        self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
+        self.spec_mem_wmask = Signal(int(self.params.xlen // 8))
-        self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
+        self.spec_mem_wdata = Signal(self.params.xlen)
 
         # Additional wires and registers
-        self.insn_padding = Signal(self.RISCV_FORMAL_ILEN)
+        self.insn_padding = Signal(self.params.ilen)
-        self.insn_imm = Signal(self.RISCV_FORMAL_XLEN)
+        self.insn_imm = Signal(self.params.xlen)
         self.insn_funct7 = Signal(7)
         self.insn_funct6 = Signal(6)
         self.insn_shamt = Signal(6)
@@ -59,7 +56,7 @@ class Insn(Elaboratable):
             self.rvfi_rs2_rdata,
             self.rvfi_mem_rdata
         ]
-        if self.RISCV_FORMAL_CSR_MISA:
+        if self.params.csr_misa:
             input_ports.append(self.rvfi_csr_misa_rdata)
         output_ports = [
             self.spec_valid,
@@ -74,7 +71,7 @@ class Insn(Elaboratable):
             self.spec_mem_wmask,
             self.spec_mem_wdata
         ]
-        if self.RISCV_FORMAL_CSR_MISA:
+        if self.params.csr_misa:
             output_ports.append(self.spec_csr_misa_rmask)
         return input_ports + output_ports
     def elaborate(self, platform):

rvfi/insns/insn_add.py

@@ -5,8 +5,8 @@ ADD instruction
 """
 
 class InsnAdd(InsnRV32IRType):
-    def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA):
+    def __init__(self, params):
-        super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, 0b0000000, 0b000, 0b0110011)
+        super().__init__(params, 0b0000000, 0b000, 0b0110011)
     def elaborate(self, platform):
         m = super().elaborate(platform)
 

rvfi/insns/insn_addi.py

@@ -5,8 +5,8 @@ ADDI instruction
 """
 
 class InsnAddi(InsnRV32IITypeArith):
-    def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA):
+    def __init__(self, params):
-        super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, 0b000)
+        super().__init__(params, 0b000)
     def elaborate(self, platform):
         m = super().elaborate(platform)
 

rvfi/insns/insn_and.py

@@ -5,8 +5,8 @@ AND instruction
 """
 
 class InsnAnd(InsnRV32IRType):
-    def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA):
+    def __init__(self, params):
-        super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, 0b0000000, 0b111, 0b0110011)
+        super().__init__(params, 0b0000000, 0b111, 0b0110011)
     def elaborate(self, platform):
         m = super().elaborate(platform)
 

rvfi/insns/insn_andi.py

@@ -5,8 +5,8 @@ ANDI instruction
 """
 
 class InsnAndi(InsnRV32IITypeArith):
-    def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA):
+    def __init__(self, params):
-        super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, 0b111)
+        super().__init__(params, 0b111)
     def elaborate(self, platform):
         m = super().elaborate(platform)
 

rvfi/insns/insn_auipc.py

@@ -5,8 +5,8 @@ AUIPC instruction
 """
 
 class InsnAuipc(InsnRV32IUType):
-    def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA):
+    def __init__(self, params):
-        super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, 0b0010111)
+        super().__init__(params, 0b0010111)
     def elaborate(self, platform):
         m = super().elaborate(platform)
 

rvfi/insns/insn_beq.py

@@ -5,12 +5,12 @@ BEQ instruction
 """
 
 class InsnBeq(InsnRV32ISBType):
-    def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED):
+    def __init__(self, params):
-        super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b000)
+        super().__init__(params, 0b000)
     def elaborate(self, platform):
         m = super().elaborate(platform)
 
-        next_pc = Signal(self.RISCV_FORMAL_XLEN)
+        next_pc = Signal(self.params.xlen)
         m.d.comb += next_pc.eq(Mux(self.rvfi_rs1_rdata == self.rvfi_rs2_rdata, self.rvfi_pc_rdata + self.insn_imm, self.rvfi_pc_rdata + 4))
         m.d.comb += self.spec_pc_wdata.eq(next_pc)
         m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok)

rvfi/insns/insn_bge.py

@@ -5,12 +5,12 @@ BGE instruction
 """
 
 class InsnBge(InsnRV32ISBType):
-    def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED):
+    def __init__(self, params):
-        super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b101)
+        super().__init__(params, 0b101)
     def elaborate(self, platform):
         m = super().elaborate(platform)
 
-        next_pc = Signal(self.RISCV_FORMAL_XLEN)
+        next_pc = Signal(self.params.xlen)
         m.d.comb += next_pc.eq(Mux(Value.as_signed(self.rvfi_rs1_rdata) >= Value.as_signed(self.rvfi_rs2_rdata), self.rvfi_pc_rdata + self.insn_imm, self.rvfi_pc_rdata + 4))
         m.d.comb += self.spec_pc_wdata.eq(next_pc)
         m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok)

rvfi/insns/insn_bgeu.py

@@ -5,12 +5,12 @@ BGEU instruction
 """
 
 class InsnBgeu(InsnRV32ISBType):
-    def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED):
+    def __init__(self, params):
-        super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b111)
+        super().__init__(params, 0b111)
     def elaborate(self, platform):
         m = super().elaborate(platform)
 
-        next_pc = Signal(self.RISCV_FORMAL_XLEN)
+        next_pc = Signal(self.params.xlen)
         m.d.comb += next_pc.eq(Mux(self.rvfi_rs1_rdata >= self.rvfi_rs2_rdata, self.rvfi_pc_rdata + self.insn_imm, self.rvfi_pc_rdata + 4))
         m.d.comb += self.spec_pc_wdata.eq(next_pc)
         m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok)

rvfi/insns/insn_blt.py

@@ -5,12 +5,12 @@ BLT instruction
 """
 
 class InsnBlt(InsnRV32ISBType):
-    def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED):
+    def __init__(self, params):
-        super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b100)
+        super().__init__(params, 0b100)
     def elaborate(self, platform):
         m = super().elaborate(platform)
 
-        next_pc = Signal(self.RISCV_FORMAL_XLEN)
+        next_pc = Signal(self.params.xlen)
         m.d.comb += next_pc.eq(Mux(Value.as_signed(self.rvfi_rs1_rdata) < Value.as_signed(self.rvfi_rs2_rdata), self.rvfi_pc_rdata + self.insn_imm, self.rvfi_pc_rdata + 4))
         m.d.comb += self.spec_pc_wdata.eq(next_pc)
         m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok)

rvfi/insns/insn_bltu.py

@@ -5,12 +5,12 @@ BLTU instruction
 """
 
 class InsnBltu(InsnRV32ISBType):
-    def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED):
+    def __init__(self, params):
-        super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b110)
+        super().__init__(params, 0b110)
     def elaborate(self, platform):
         m = super().elaborate(platform)
 
-        next_pc = Signal(self.RISCV_FORMAL_XLEN)
+        next_pc = Signal(self.params.xlen)
         m.d.comb += next_pc.eq(Mux(self.rvfi_rs1_rdata < self.rvfi_rs2_rdata, self.rvfi_pc_rdata + self.insn_imm, self.rvfi_pc_rdata + 4))
         m.d.comb += self.spec_pc_wdata.eq(next_pc)
         m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok)

rvfi/insns/insn_bne.py

@@ -5,12 +5,12 @@ BNE instruction
 """
 
 class InsnBne(InsnRV32ISBType):
-    def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED):
+    def __init__(self, params):
-        super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b001)
+        super().__init__(params, 0b001)
     def elaborate(self, platform):
         m = super().elaborate(platform)
 
-        next_pc = Signal(self.RISCV_FORMAL_XLEN)
+        next_pc = Signal(self.params.xlen)
         m.d.comb += next_pc.eq(Mux(self.rvfi_rs1_rdata != self.rvfi_rs2_rdata, self.rvfi_pc_rdata + self.insn_imm, self.rvfi_pc_rdata + 4))
         m.d.comb += self.spec_pc_wdata.eq(next_pc)
         m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok)

rvfi/insns/insn_jal.py

@@ -5,26 +5,23 @@ JAL instruction
 """
 
 class InsnJal(Insn):
-    def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED):
-        super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA)
-        self.RISCV_FORMAL_COMPRESSED = RISCV_FORMAL_COMPRESSED
     def elaborate(self, platform):
         m = super().elaborate(platform)
 
         m.d.comb += self.insn_imm.eq(Value.as_signed(Cat(self.rvfi_insn[21:31], self.rvfi_insn[20], self.rvfi_insn[12:20], self.rvfi_insn[31]) << 1))
 
-        if self.RISCV_FORMAL_CSR_MISA:
+        if self.params.csr_misa:
             m.d.comb += self.misa_ok.eq((self.rvfi_csr_misa_rdata & 0) == 0)
             m.d.comb += self.spec_csr_misa_rmask.eq(4)
             m.d.comb += self.ialign16.eq((self.rvfi_csr_misa_rdata & 4) != 0)
         else:
             m.d.comb += self.misa_ok.eq(1)
-            if self.RISCV_FORMAL_COMPRESSED:
+            if self.params.compressed:
                 m.d.comb += self.ialign16.eq(1)
             else:
                 m.d.comb += self.ialign16.eq(0)
 
-        next_pc = Signal(self.RISCV_FORMAL_XLEN)
+        next_pc = Signal(self.params.xlen)
         m.d.comb += next_pc.eq(self.rvfi_rs1_rdata + self.insn_imm)
         m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_opcode == 0b1101111))
         m.d.comb += self.spec_rd_addr.eq(self.insn_rd)

rvfi/insns/insn_jalr.py

@@ -5,24 +5,21 @@ JALR instruction
 """
 
 class InsnJalr(InsnRV32IIType):
-    def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED):
-        super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA)
-        self.RISCV_FORMAL_COMPRESSED = RISCV_FORMAL_COMPRESSED
     def elaborate(self, platform):
         m = super().elaborate(platform)
 
-        if self.RISCV_FORMAL_CSR_MISA:
+        if self.params.csr_misa:
             m.d.comb += self.misa_ok.eq((self.rvfi_csr_misa_rdata & 0) == 0)
             m.d.comb += self.spec_csr_misa_rmask.eq(4)
             m.d.comb += self.ialign16.eq((self.rvfi_csr_misa_rdata & 4) != 0)
         else:
             m.d.comb += self.misa_ok.eq(1)
-            if self.RISCV_FORMAL_COMPRESSED:
+            if self.params.compressed:
                 m.d.comb += self.ialign16.eq(1)
             else:
                 m.d.comb += self.ialign16.eq(0)
 
-        next_pc = Signal(self.RISCV_FORMAL_XLEN)
+        next_pc = Signal(self.params.xlen)
         m.d.comb += next_pc.eq((self.rvfi_rs1_rdata + self.insn_imm) & ~1)
         m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b000) & (self.insn_opcode == 0b1100111))
         m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)

rvfi/insns/insn_lb.py

@@ -5,5 +5,5 @@ LB instruction
 """
 
 class InsnLb(InsnRV32IITypeLoad):
-    def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_ALIGNED_MEM):
+    def __init__(self, params):
-        super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_ALIGNED_MEM, 0b000, 1, True)
+        super().__init__(params, 0b000, 1, True)

rvfi/insns/insn_lbu.py

@@ -5,5 +5,5 @@ LBU instruction
 """
 
 class InsnLbu(InsnRV32IITypeLoad):
-    def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_ALIGNED_MEM):
+    def __init__(self, params):
-        super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_ALIGNED_MEM, 0b100, 1, False)
+        super().__init__(params, 0b100, 1, False)

rvfi/insns/insn_lh.py

@@ -5,5 +5,5 @@ LH instruction
 """
 
 class InsnLh(InsnRV32IITypeLoad):
-    def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_ALIGNED_MEM):
+    def __init__(self, params):
-        super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_ALIGNED_MEM, 0b001, 2, True)
+        super().__init__(params, 0b001, 2, True)

rvfi/insns/insn_lhu.py

@@ -5,5 +5,5 @@ LHU instruction
 """
 
 class InsnLhu(InsnRV32IITypeLoad):
-    def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_ALIGNED_MEM):
+    def __init__(self, params):
-        super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_ALIGNED_MEM, 0b101, 2, False)
+        super().__init__(params, 0b101, 2, False)

rvfi/insns/insn_lui.py

@@ -5,8 +5,8 @@ LUI instruction
 """
 
 class InsnLui(InsnRV32IUType):
-    def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA):
+    def __init__(self, params):
-        super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, 0b0110111)
+        super().__init__(params, 0b0110111)
     def elaborate(self, platform):
         m = super().elaborate(platform)
 

rvfi/insns/insn_lw.py

@@ -5,5 +5,5 @@ LW instruction
 """
 
 class InsnLw(InsnRV32IITypeLoad):
-    def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_ALIGNED_MEM):
+    def __init__(self, params):
-        super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_ALIGNED_MEM, 0b010, 4, True)
+        super().__init__(params, 0b010, 4, True)

rvfi/insns/insn_or.py

@@ -5,8 +5,8 @@ OR instruction
 """
 
 class InsnOr(InsnRV32IRType):
-    def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA):
+    def __init__(self, params):
-        super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, 0b0000000, 0b110, 0b0110011)
+        super().__init__(params, 0b0000000, 0b110, 0b0110011)
     def elaborate(self, platform):
         m = super().elaborate(platform)
 

rvfi/insns/insn_ori.py

@@ -5,8 +5,8 @@ ORI instruction
 """
 
 class InsnOri(InsnRV32IITypeArith):
-    def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA):
+    def __init__(self, params):
-        super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, 0b110)
+        super().__init__(params, 0b110)
     def elaborate(self, platform):
         m = super().elaborate(platform)
 

rvfi/insns/insn_rv32i_i_type_arith.py

@@ -5,13 +5,13 @@ RV32I I-Type Instruction (Arithmetic Variation)
 """
 
 class InsnRV32IITypeArith(InsnRV32IIType):
-    def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, funct3):
+    def __init__(self, params, funct3):
-        super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA)
+        super().__init__(params)
         self.funct3 = funct3
     def elaborate(self, platform):
         m = super().elaborate(platform)
 
-        if self.RISCV_FORMAL_CSR_MISA:
+        if self.params.csr_misa:
             m.d.comb += self.misa_ok.eq((self.rvfi_csr_misa_rdata & 0) == 0)
             m.d.comb += self.spec_csr_misa_rmask.eq(0)
         else:

rvfi/insns/insn_rv32i_i_type_load.py

@@ -5,30 +5,29 @@ RV32I I-Type Instruction (Load Variation)
 """
 
 class InsnRV32IITypeLoad(InsnRV32IIType):
-    def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_ALIGNED_MEM, funct3, mask_shift, is_signed):
+    def __init__(self, params, funct3, mask_shift, is_signed):
-        super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA)
+        super().__init__(params)
-        self.RISCV_FORMAL_ALIGNED_MEM = RISCV_FORMAL_ALIGNED_MEM
         self.funct3 = funct3
         self.mask_shift = mask_shift
         self.is_signed = is_signed
-        self.addr = Signal(self.RISCV_FORMAL_XLEN)
+        self.addr = Signal(self.params.xlen)
         self.result = Signal(8 * self.mask_shift)
     def elaborate(self, platform):
         m = super().elaborate(platform)
 
-        if self.RISCV_FORMAL_CSR_MISA:
+        if self.params.csr_misa:
             m.d.comb += self.misa_ok.eq((self.rvfi_csr_misa_rdata & 0) == 0)
             m.d.comb += self.spec_csr_misa_rmask.eq(0)
         else:
             m.d.comb += self.misa_ok.eq(1)
 
-        if self.RISCV_FORMAL_ALIGNED_MEM:
+        if self.params.aligned_mem:
             m.d.comb += self.addr.eq(self.rvfi_rs1_rdata + self.insn_imm)
             m.d.comb += self.result.eq(self.rvfi_mem_rdata >> (8 * (self.addr - self.spec_mem_addr)))
             m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == self.funct3) & (self.insn_opcode == 0b0000011))
             m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
             m.d.comb += self.spec_rd_addr.eq(self.insn_rd)
-            m.d.comb += self.spec_mem_addr.eq(self.addr & ~(int(self.RISCV_FORMAL_XLEN // 8) - 1))
+            m.d.comb += self.spec_mem_addr.eq(self.addr & ~(int(self.params.xlen // 8) - 1))
             m.d.comb += self.spec_mem_rmask.eq(((1 << self.mask_shift) - 1) << (self.addr - self.spec_mem_addr))
             m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, Value.as_signed(self.result) if self.is_signed else self.result, 0))
             m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)

rvfi/insns/insn_rv32i_i_type_shift.py

@@ -5,20 +5,20 @@ RV32I I-Type Instruction (Shift Variation)
 """
 
 class InsnRV32IITypeShift(Insn):
-    def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, funct6, funct3):
+    def __init__(self, params, funct6, funct3):
-        super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA)
+        super().__init__(params)
         self.funct6 = funct6
         self.funct3 = funct3
     def elaborate(self, platform):
         m = super().elaborate(platform)
 
-        if self.RISCV_FORMAL_CSR_MISA:
+        if self.params.csr_misa:
             m.d.comb += self.misa_ok.eq((self.rvfi_csr_misa_rdata & 0) == 0)
             m.d.comb += self.spec_csr_misa_rmask.eq(0)
         else:
             m.d.comb += self.misa_ok.eq(1)
 
-        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct6 == self.funct6) & (self.insn_funct3 == self.funct3) & (self.insn_opcode == 0b0010011) & ((~self.insn_shamt[5]) | (self.RISCV_FORMAL_XLEN == 64)))
+        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct6 == self.funct6) & (self.insn_funct3 == self.funct3) & (self.insn_opcode == 0b0010011) & ((~self.insn_shamt[5]) | (self.params.xlen == 64)))
         m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
         m.d.comb += self.spec_rd_addr.eq(self.insn_rd)
         m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)

rvfi/insns/insn_rv32i_r_type.py

@@ -5,15 +5,15 @@ RV32I R-Type Instruction
 """
 
 class InsnRV32IRType(Insn):
-    def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, funct7, funct3, opcode):
+    def __init__(self, params, funct7, funct3, opcode):
-        super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA)
+        super().__init__(params)
         self.funct7 = funct7
         self.funct3 = funct3
         self.opcode = opcode
     def elaborate(self, platform):
         m = super().elaborate(platform)
 
-        if self.RISCV_FORMAL_CSR_MISA:
+        if self.params.csr_misa:
             m.d.comb += self.misa_ok.eq((self.rvfi_csr_misa_rdata & 0) == 0)
             m.d.comb += self.spec_csr_misa_rmask.eq(0)
         else:

rvfi/insns/insn_rv32i_s_type.py

@@ -5,29 +5,28 @@ RV32I S-Type Instruction
 """
 
 class InsnRV32ISType(Insn):
-    def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_ALIGNED_MEM, funct3, mask_shift):
+    def __init__(self, params, funct3, mask_shift):
-        super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA)
+        super().__init__(params)
-        self.RISCV_FORMAL_ALIGNED_MEM = RISCV_FORMAL_ALIGNED_MEM
         self.funct3 = funct3
         self.mask_shift = mask_shift
-        self.addr = Signal(self.RISCV_FORMAL_XLEN)
+        self.addr = Signal(self.params.xlen)
     def elaborate(self, platform):
         m = super().elaborate(platform)
 
         m.d.comb += self.insn_imm.eq(Value.as_signed(Cat(self.rvfi_insn[7:12], self.rvfi_insn[25:32])))
         
-        if self.RISCV_FORMAL_CSR_MISA:
+        if self.params.csr_misa:
             m.d.comb += self.misa_ok.eq((self.rvfi_csr_misa_rdata & 0) == 0)
             m.d.comb += self.spec_csr_misa_rmask.eq(0)
         else:
             m.d.comb += self.misa_ok.eq(1)
 
-        if self.RISCV_FORMAL_ALIGNED_MEM:
+        if self.params.aligned_mem:
             m.d.comb += self.addr.eq(self.rvfi_rs1_rdata + self.insn_imm)
             m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == self.funct3) & (self.insn_opcode == 0b0100011))
             m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
             m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2)
-            m.d.comb += self.spec_mem_addr.eq(self.addr & ~(int(self.RISCV_FORMAL_XLEN // 8) - 1))
+            m.d.comb += self.spec_mem_addr.eq(self.addr & ~(int(self.params.xlen // 8) - 1))
             m.d.comb += self.spec_mem_wmask.eq(((1 << self.mask_shift) - 1) << (self.addr - self.spec_mem_addr))
             m.d.comb += self.spec_mem_wdata.eq(self.rvfi_rs2_rdata << (8 * (self.addr - self.spec_mem_addr)))
             m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)

rvfi/insns/insn_rv32i_sb_type.py

@@ -5,22 +5,21 @@ RV32I SB-Type Instruction
 """
 
 class InsnRV32ISBType(Insn):
-    def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, funct3):
+    def __init__(self, params, funct3):
-        super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA)
+        super().__init__(params)
-        self.RISCV_FORMAL_COMPRESSED = RISCV_FORMAL_COMPRESSED
         self.funct3 = funct3
     def elaborate(self, platform):
         m = super().elaborate(platform)
 
         m.d.comb += self.insn_imm.eq(Value.as_signed(Cat(self.rvfi_insn[8:12], self.rvfi_insn[25:31], self.rvfi_insn[7], self.rvfi_insn[31]) << 1))
 
-        if self.RISCV_FORMAL_CSR_MISA:
+        if self.params.csr_misa:
             m.d.comb += self.misa_ok.eq((self.rvfi_csr_misa_rdata & 0) == 0)
             m.d.comb += self.spec_csr_misa_rmask.eq(4)
             m.d.comb += self.ialign16.eq((self.rvfi_csr_misa_rdata & 4) != 0)
         else:
             m.d.comb += self.misa_ok.eq(1)
-            if self.RISCV_FORMAL_COMPRESSED:
+            if self.params.compressed:
                 m.d.comb += self.ialign16.eq(1)
             else:
                 m.d.comb += self.ialign16.eq(0)

rvfi/insns/insn_rv32i_u_type.py

@@ -5,15 +5,15 @@ RV32I U-Type Instruction
 """
 
 class InsnRV32IUType(Insn):
-    def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, opcode):
+    def __init__(self, params, opcode):
-        super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA)
+        super().__init__(params)
         self.opcode = opcode
     def elaborate(self, platform):
         m = super().elaborate(platform)
 
         m.d.comb += self.insn_imm.eq(Value.as_signed(self.rvfi_insn[12:32] << 12))
 
-        if self.RISCV_FORMAL_CSR_MISA:
+        if self.params.csr_misa:
             m.d.comb += self.misa_ok.eq((self.rvfi_csr_misa_rdata & 0) == 0)
             m.d.comb += self.spec_csr_misa_rmask.eq(0)
         else:

rvfi/insns/insn_sb.py

@@ -5,5 +5,5 @@ SB instruction
 """
 
 class InsnSb(InsnRV32ISType):
-    def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_ALIGNED_MEM):
+    def __init__(self, params):
-        super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_ALIGNED_MEM, 0b000, 1)
+        super().__init__(params, 0b000, 1)

rvfi/insns/insn_sh.py

@@ -5,5 +5,5 @@ SH instruction
 """
 
 class InsnSh(InsnRV32ISType):
-    def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_ALIGNED_MEM):
+    def __init__(self, params):
-        super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_ALIGNED_MEM, 0b001, 2)
+        super().__init__(params, 0b001, 2)

rvfi/insns/insn_sll.py

@@ -5,8 +5,8 @@ SLL instruction
 """
 
 class InsnSll(InsnRV32IRType):
-    def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA):
+    def __init__(self, params):
-        super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, 0b0000000, 0b001, 0b0110011)
+        super().__init__(params, 0b0000000, 0b001, 0b0110011)
     def elaborate(self, platform):
         m = super().elaborate(platform)
 

rvfi/insns/insn_slli.py

@@ -5,8 +5,8 @@ SLLI instruction
 """
 
 class InsnSlli(InsnRV32IITypeShift):
-    def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA):
+    def __init__(self, params):
-        super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, 0b000000, 0b001)
+        super().__init__(params, 0b000000, 0b001)
     def elaborate(self, platform):
         m = super().elaborate(platform)
 

rvfi/insns/insn_slt.py

@@ -5,8 +5,8 @@ SLT instruction
 """
 
 class InsnSlt(InsnRV32IRType):
-    def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA):
+    def __init__(self, params):
-        super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, 0b0000000, 0b010, 0b0110011)
+        super().__init__(params, 0b0000000, 0b010, 0b0110011)
     def elaborate(self, platform):
         m = super().elaborate(platform)
 

rvfi/insns/insn_slti.py

@@ -5,8 +5,8 @@ SLTI instruction
 """
 
 class InsnSlti(InsnRV32IITypeArith):
-    def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA):
+    def __init__(self, params):
-        super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, 0b010)
+        super().__init__(params, 0b010)
     def elaborate(self, platform):
         m = super().elaborate(platform)
 

rvfi/insns/insn_sltiu.py

@@ -5,8 +5,8 @@ SLTIU instruction
 """
 
 class InsnSltiu(InsnRV32IITypeArith):
-    def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA):
+    def __init__(self, params):
-        super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, 0b011)
+        super().__init__(params, 0b011)
     def elaborate(self, platform):
         m = super().elaborate(platform)
 

rvfi/insns/insn_sltu.py

@@ -5,8 +5,8 @@ SLTU instruction
 """
 
 class InsnSltu(InsnRV32IRType):
-    def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA):
+    def __init__(self, params):
-        super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, 0b0000000, 0b011, 0b0110011)
+        super().__init__(params, 0b0000000, 0b011, 0b0110011)
     def elaborate(self, platform):
         m = super().elaborate(platform)
 

rvfi/insns/insn_sra.py

@@ -5,8 +5,8 @@ SRA instruction
 """
 
 class InsnSra(InsnRV32IRType):
-    def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA):
+    def __init__(self, params):
-        super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, 0b0100000, 0b101, 0b0110011)
+        super().__init__(params, 0b0100000, 0b101, 0b0110011)
     def elaborate(self, platform):
         m = super().elaborate(platform)
 

rvfi/insns/insn_srai.py

@@ -5,8 +5,8 @@ SRAI instruction
 """
 
 class InsnSrai(InsnRV32IITypeShift):
-    def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA):
+    def __init__(self, params):
-        super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, 0b010000, 0b101)
+        super().__init__(params, 0b010000, 0b101)
     def elaborate(self, platform):
         m = super().elaborate(platform)
 

rvfi/insns/insn_srl.py

@@ -5,8 +5,8 @@ SRL instruction
 """
 
 class InsnSrl(InsnRV32IRType):
-    def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA):
+    def __init__(self, params):
-        super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, 0b0000000, 0b100, 0b0110011)
+        super().__init__(params, 0b0000000, 0b100, 0b0110011)
     def elaborate(self, platform):
         m = super().elaborate(platform)
 

rvfi/insns/insn_srli.py

@@ -5,8 +5,8 @@ SRLI instruction
 """
 
 class InsnSrli(InsnRV32IITypeShift):
-    def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA):
+    def __init__(self, params):
-        super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, 0b000000, 0b101)
+        super().__init__(params, 0b000000, 0b101)
     def elaborate(self, platform):
         m = super().elaborate(platform)
 

rvfi/insns/insn_sub.py

@@ -5,8 +5,8 @@ SUB instruction
 """
 
 class InsnSub(InsnRV32IRType):
-    def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA):
+    def __init__(self, params):
-        super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, 0b0100000, 0b000, 0b0110011)
+        super().__init__(params, 0b0100000, 0b000, 0b0110011)
     def elaborate(self, platform):
         m = super().elaborate(platform)
 

rvfi/insns/insn_sw.py

@@ -5,5 +5,5 @@ SW instruction
 """
 
 class InsnSw(InsnRV32ISType):
-    def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_ALIGNED_MEM):
+    def __init__(self, params):
-        super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_ALIGNED_MEM, 0b010, 4)
+        super().__init__(params, 0b010, 4)

rvfi/insns/insn_xor.py

@@ -5,8 +5,8 @@ XOR instruction
 """
 
 class InsnXor(InsnRV32IRType):
-    def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA):
+    def __init__(self, params):
-        super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, 0b0000000, 0b100, 0b0110011)
+        super().__init__(params, 0b0000000, 0b100, 0b0110011)
     def elaborate(self, platform):
         m = super().elaborate(platform)
 

rvfi/insns/insn_xori.py

@@ -5,8 +5,8 @@ XORI instruction
 """
 
 class InsnXori(InsnRV32IITypeArith):
-    def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA):
+    def __init__(self, params):
-        super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, 0b100)
+        super().__init__(params, 0b100)
     def elaborate(self, platform):
         m = super().elaborate(platform)
 

rvfi/riscv_formal_parameters.py

@@ -0,0 +1,4 @@
+from collections import namedtuple
+
+RISCVFormalParameters = namedtuple('RISCVFormalParameters',
+    ['ilen', 'xlen', 'csr_misa', 'compressed', 'aligned_mem'])