Add RV32IM ISA
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5bce84836c
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2421f1f6b6
1459
insns/isa_rv32im.py
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1459
insns/isa_rv32im.py
Normal file
File diff suppressed because it is too large
Load Diff
45
insns/isa_rv32im.txt
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45
insns/isa_rv32im.txt
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lui
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auipc
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jal
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jalr
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beq
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bne
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blt
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bge
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bltu
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bgeu
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lb
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lh
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lw
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lbu
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lhu
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sb
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sh
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sw
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addi
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slti
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sltiu
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xori
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ori
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andi
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slli
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srli
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srai
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add
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sub
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sll
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slt
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sltu
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xor
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srl
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sra
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or
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and
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mul
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mulh
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mulhsu
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mulhu
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div
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divu
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rem
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remu
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107
insns/isa_rv32im_gen.py
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107
insns/isa_rv32im_gen.py
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with open('isa_rv32im.py', 'w') as isa_rv32im:
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def fprint(strng):
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print(strng, file=isa_rv32im)
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fprint("# Generated by isa_rv32im_gen.py")
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fprint("from nmigen import *")
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with open('isa_rv32im.txt', 'r') as isa_rv32im_txt_file:
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isa_rv32im_insns = isa_rv32im_txt_file.read().split('\n')[:-1]
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for isa_rv32im_insn in isa_rv32im_insns:
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fprint("from insn_%s import *" % isa_rv32im_insn)
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fprint("")
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fprint("class rvfi_isa_rv32im(Elaboratable):")
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fprint(" def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):")
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fprint(" self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN")
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fprint(" self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN")
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fprint(" self.rvfi_valid = Signal(1)")
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fprint(" self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)")
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fprint(" self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)")
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fprint(" self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)")
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fprint(" self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)")
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fprint(" self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)")
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fprint("")
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fprint(" self.spec_valid = Signal(1)")
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fprint(" self.spec_trap = Signal(1)")
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fprint(" self.spec_rs1_addr = Signal(5)")
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fprint(" self.spec_rs2_addr = Signal(5)")
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fprint(" self.spec_rd_addr = Signal(5)")
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fprint(" self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)")
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fprint(" self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)")
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fprint(" self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)")
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fprint(" self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))")
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fprint(" self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))")
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fprint(" self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)")
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fprint(" def ports(self):")
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fprint(" input_ports = [")
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fprint(" self.rvfi_valid,")
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fprint(" self.rvfi_insn,")
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fprint(" self.rvfi_pc_rdata,")
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fprint(" self.rvfi_rs1_rdata,")
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fprint(" self.rvfi_rs2_rdata,")
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fprint(" self.rvfi_mem_rdata")
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fprint(" ]")
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fprint(" output_ports = [")
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fprint(" self.spec_valid,")
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fprint(" self.spec_trap,")
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fprint(" self.spec_rs1_addr,")
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fprint(" self.spec_rs2_addr,")
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fprint(" self.spec_rd_addr,")
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fprint(" self.spec_rd_wdata,")
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fprint(" self.spec_pc_wdata,")
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fprint(" self.spec_mem_addr,")
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fprint(" self.spec_mem_rmask,")
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fprint(" self.spec_mem_wmask,")
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fprint(" self.spec_mem_wdata")
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fprint(" ]")
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fprint(" return input_ports + output_ports")
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fprint(" def elaborate(self, platform):")
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fprint(" m = Module()")
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fprint("")
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for isa_rv32im_insn in isa_rv32im_insns:
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fprint(" spec_insn_%s_valid = Signal(1)" % isa_rv32im_insn)
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fprint(" spec_insn_%s_trap = Signal(1)" % isa_rv32im_insn)
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fprint(" spec_insn_%s_rs1_addr = Signal(5)" % isa_rv32im_insn)
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fprint(" spec_insn_%s_rs2_addr = Signal(5)" % isa_rv32im_insn)
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fprint(" spec_insn_%s_rd_addr = Signal(5)" % isa_rv32im_insn)
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fprint(" spec_insn_%s_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)" % isa_rv32im_insn)
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fprint(" spec_insn_%s_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)" % isa_rv32im_insn)
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fprint(" spec_insn_%s_mem_addr = Signal(self.RISCV_FORMAL_XLEN)" % isa_rv32im_insn)
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fprint(" spec_insn_%s_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))" % isa_rv32im_insn)
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fprint(" spec_insn_%s_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))" % isa_rv32im_insn)
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fprint(" spec_insn_%s_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)" % isa_rv32im_insn)
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fprint(" m.submodules.insn_%s = insn_%s = rvfi_insn_%s()" % (isa_rv32im_insn, isa_rv32im_insn, isa_rv32im_insn))
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fprint(" m.d.comb += insn_%s.rvfi_valid.eq(self.rvfi_valid)" % isa_rv32im_insn)
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fprint(" m.d.comb += insn_%s.rvfi_insn.eq(self.rvfi_insn)" % isa_rv32im_insn)
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fprint(" m.d.comb += insn_%s.rvfi_pc_rdata.eq(self.rvfi_pc_rdata)" % isa_rv32im_insn)
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fprint(" m.d.comb += insn_%s.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata)" % isa_rv32im_insn)
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fprint(" m.d.comb += insn_%s.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata)" % isa_rv32im_insn)
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fprint(" m.d.comb += insn_%s.rvfi_mem_rdata.eq(self.rvfi_mem_rdata)" % isa_rv32im_insn)
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fprint(" m.d.comb += spec_insn_%s_valid.eq(insn_%s.spec_valid)" % (isa_rv32im_insn, isa_rv32im_insn))
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fprint(" m.d.comb += spec_insn_%s_trap.eq(insn_%s.spec_trap)" % (isa_rv32im_insn, isa_rv32im_insn))
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fprint(" m.d.comb += spec_insn_%s_rs1_addr.eq(insn_%s.spec_rs1_addr)" % (isa_rv32im_insn, isa_rv32im_insn))
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fprint(" m.d.comb += spec_insn_%s_rs2_addr.eq(insn_%s.spec_rs2_addr)" % (isa_rv32im_insn, isa_rv32im_insn))
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fprint(" m.d.comb += spec_insn_%s_rd_addr.eq(insn_%s.spec_rd_addr)" % (isa_rv32im_insn, isa_rv32im_insn))
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fprint(" m.d.comb += spec_insn_%s_rd_wdata.eq(insn_%s.spec_rd_wdata)" % (isa_rv32im_insn, isa_rv32im_insn))
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fprint(" m.d.comb += spec_insn_%s_pc_wdata.eq(insn_%s.spec_pc_wdata)" % (isa_rv32im_insn, isa_rv32im_insn))
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fprint(" m.d.comb += spec_insn_%s_mem_addr.eq(insn_%s.spec_mem_addr)" % (isa_rv32im_insn, isa_rv32im_insn))
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fprint(" m.d.comb += spec_insn_%s_mem_rmask.eq(insn_%s.spec_mem_rmask)" % (isa_rv32im_insn, isa_rv32im_insn))
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fprint(" m.d.comb += spec_insn_%s_mem_wmask.eq(insn_%s.spec_mem_wmask)" % (isa_rv32im_insn, isa_rv32im_insn))
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fprint(" m.d.comb += spec_insn_%s_mem_wdata.eq(insn_%s.spec_mem_wdata)" % (isa_rv32im_insn, isa_rv32im_insn))
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fprint("")
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def gen_spec(strng):
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result = "0"
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for isa_rv32im_insn in isa_rv32im_insns:
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result = "Mux(spec_insn_%s_valid, spec_insn_%s_%s, %s)" % (isa_rv32im_insn, isa_rv32im_insn, strng, result)
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fprint(" m.d.comb += self.spec_%s.eq(%s)" % (strng, result))
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gen_spec("valid")
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gen_spec("trap")
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gen_spec("rs1_addr")
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gen_spec("rs2_addr")
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gen_spec("rd_addr")
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gen_spec("rd_wdata")
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gen_spec("pc_wdata")
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gen_spec("mem_addr")
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gen_spec("mem_rmask")
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gen_spec("mem_wmask")
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gen_spec("mem_wdata")
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fprint("")
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fprint(" return m")
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