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riscv-formal-nmigen
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Add BLT instruction

This commit is contained in:
Donald Sebastian Leung 2020-08-11 16:52:34 +08:00
parent 1cff0134fe
commit 17816f9464
1 changed files with 18 additions and 0 deletions
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insns/InsnBlt.py Normal file
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from InsnRV32ISBType import *
"""
BLT instruction
"""
class InsnBlt(InsnRV32ISBType):
def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED):
super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b100)
def elaborate(self, platform):
m = super().elaborate(platform)
next_pc = Signal(self.RISCV_FORMAL_XLEN)
m.d.comb += next_pc.eq(Mux(Value.as_signed(self.rvfi_rs1_rdata) < Value.as_signed(self.rvfi_rs2_rdata), self.rvfi_pc_rdata + self.insn_imm, self.rvfi_pc_rdata + 4))
m.d.comb += self.spec_pc_wdata.eq(next_pc)
m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok)
return m