1460 lines
108 KiB
Python
1460 lines
108 KiB
Python
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# Generated by isa_rv32im_gen.py
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from nmigen import *
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from insn_lui import *
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from insn_auipc import *
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from insn_jal import *
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from insn_jalr import *
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from insn_beq import *
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from insn_bne import *
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from insn_blt import *
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from insn_bge import *
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from insn_bltu import *
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from insn_bgeu import *
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from insn_lb import *
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from insn_lh import *
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from insn_lw import *
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from insn_lbu import *
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from insn_lhu import *
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from insn_sb import *
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from insn_sh import *
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from insn_sw import *
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from insn_addi import *
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from insn_slti import *
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from insn_sltiu import *
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from insn_xori import *
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from insn_ori import *
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from insn_andi import *
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from insn_slli import *
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from insn_srli import *
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from insn_srai import *
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from insn_add import *
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from insn_sub import *
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from insn_sll import *
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from insn_slt import *
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from insn_sltu import *
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from insn_xor import *
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from insn_srl import *
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from insn_sra import *
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from insn_or import *
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from insn_and import *
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from insn_mul import *
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from insn_mulh import *
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from insn_mulhsu import *
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from insn_mulhu import *
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from insn_div import *
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from insn_divu import *
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from insn_rem import *
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from insn_remu import *
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class rvfi_isa_rv32im(Elaboratable):
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def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
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self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
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self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
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self.rvfi_valid = Signal(1)
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self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
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self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
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self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
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self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
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self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
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self.spec_valid = Signal(1)
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self.spec_trap = Signal(1)
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self.spec_rs1_addr = Signal(5)
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self.spec_rs2_addr = Signal(5)
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self.spec_rd_addr = Signal(5)
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self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
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self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
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self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
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self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
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self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
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self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
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def ports(self):
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input_ports = [
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self.rvfi_valid,
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self.rvfi_insn,
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self.rvfi_pc_rdata,
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self.rvfi_rs1_rdata,
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self.rvfi_rs2_rdata,
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self.rvfi_mem_rdata
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]
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output_ports = [
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self.spec_valid,
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self.spec_trap,
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self.spec_rs1_addr,
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self.spec_rs2_addr,
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self.spec_rd_addr,
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self.spec_rd_wdata,
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self.spec_pc_wdata,
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self.spec_mem_addr,
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self.spec_mem_rmask,
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self.spec_mem_wmask,
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self.spec_mem_wdata
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]
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return input_ports + output_ports
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def elaborate(self, platform):
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m = Module()
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spec_insn_lui_valid = Signal(1)
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spec_insn_lui_trap = Signal(1)
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spec_insn_lui_rs1_addr = Signal(5)
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spec_insn_lui_rs2_addr = Signal(5)
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spec_insn_lui_rd_addr = Signal(5)
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spec_insn_lui_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
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spec_insn_lui_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
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spec_insn_lui_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
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spec_insn_lui_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
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spec_insn_lui_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
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spec_insn_lui_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
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m.submodules.insn_lui = insn_lui = rvfi_insn_lui()
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m.d.comb += insn_lui.rvfi_valid.eq(self.rvfi_valid)
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m.d.comb += insn_lui.rvfi_insn.eq(self.rvfi_insn)
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m.d.comb += insn_lui.rvfi_pc_rdata.eq(self.rvfi_pc_rdata)
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m.d.comb += insn_lui.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata)
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m.d.comb += insn_lui.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata)
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m.d.comb += insn_lui.rvfi_mem_rdata.eq(self.rvfi_mem_rdata)
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m.d.comb += spec_insn_lui_valid.eq(insn_lui.spec_valid)
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m.d.comb += spec_insn_lui_trap.eq(insn_lui.spec_trap)
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m.d.comb += spec_insn_lui_rs1_addr.eq(insn_lui.spec_rs1_addr)
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m.d.comb += spec_insn_lui_rs2_addr.eq(insn_lui.spec_rs2_addr)
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m.d.comb += spec_insn_lui_rd_addr.eq(insn_lui.spec_rd_addr)
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m.d.comb += spec_insn_lui_rd_wdata.eq(insn_lui.spec_rd_wdata)
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m.d.comb += spec_insn_lui_pc_wdata.eq(insn_lui.spec_pc_wdata)
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m.d.comb += spec_insn_lui_mem_addr.eq(insn_lui.spec_mem_addr)
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m.d.comb += spec_insn_lui_mem_rmask.eq(insn_lui.spec_mem_rmask)
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m.d.comb += spec_insn_lui_mem_wmask.eq(insn_lui.spec_mem_wmask)
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m.d.comb += spec_insn_lui_mem_wdata.eq(insn_lui.spec_mem_wdata)
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spec_insn_auipc_valid = Signal(1)
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spec_insn_auipc_trap = Signal(1)
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spec_insn_auipc_rs1_addr = Signal(5)
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spec_insn_auipc_rs2_addr = Signal(5)
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spec_insn_auipc_rd_addr = Signal(5)
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spec_insn_auipc_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
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spec_insn_auipc_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
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spec_insn_auipc_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
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spec_insn_auipc_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
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spec_insn_auipc_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
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spec_insn_auipc_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
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m.submodules.insn_auipc = insn_auipc = rvfi_insn_auipc()
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m.d.comb += insn_auipc.rvfi_valid.eq(self.rvfi_valid)
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m.d.comb += insn_auipc.rvfi_insn.eq(self.rvfi_insn)
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m.d.comb += insn_auipc.rvfi_pc_rdata.eq(self.rvfi_pc_rdata)
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m.d.comb += insn_auipc.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata)
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m.d.comb += insn_auipc.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata)
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m.d.comb += insn_auipc.rvfi_mem_rdata.eq(self.rvfi_mem_rdata)
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m.d.comb += spec_insn_auipc_valid.eq(insn_auipc.spec_valid)
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m.d.comb += spec_insn_auipc_trap.eq(insn_auipc.spec_trap)
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m.d.comb += spec_insn_auipc_rs1_addr.eq(insn_auipc.spec_rs1_addr)
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m.d.comb += spec_insn_auipc_rs2_addr.eq(insn_auipc.spec_rs2_addr)
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m.d.comb += spec_insn_auipc_rd_addr.eq(insn_auipc.spec_rd_addr)
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m.d.comb += spec_insn_auipc_rd_wdata.eq(insn_auipc.spec_rd_wdata)
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m.d.comb += spec_insn_auipc_pc_wdata.eq(insn_auipc.spec_pc_wdata)
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m.d.comb += spec_insn_auipc_mem_addr.eq(insn_auipc.spec_mem_addr)
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m.d.comb += spec_insn_auipc_mem_rmask.eq(insn_auipc.spec_mem_rmask)
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m.d.comb += spec_insn_auipc_mem_wmask.eq(insn_auipc.spec_mem_wmask)
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m.d.comb += spec_insn_auipc_mem_wdata.eq(insn_auipc.spec_mem_wdata)
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spec_insn_jal_valid = Signal(1)
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spec_insn_jal_trap = Signal(1)
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spec_insn_jal_rs1_addr = Signal(5)
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spec_insn_jal_rs2_addr = Signal(5)
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spec_insn_jal_rd_addr = Signal(5)
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spec_insn_jal_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
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spec_insn_jal_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
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spec_insn_jal_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
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spec_insn_jal_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
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spec_insn_jal_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
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spec_insn_jal_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
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m.submodules.insn_jal = insn_jal = rvfi_insn_jal()
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m.d.comb += insn_jal.rvfi_valid.eq(self.rvfi_valid)
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m.d.comb += insn_jal.rvfi_insn.eq(self.rvfi_insn)
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m.d.comb += insn_jal.rvfi_pc_rdata.eq(self.rvfi_pc_rdata)
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m.d.comb += insn_jal.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata)
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m.d.comb += insn_jal.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata)
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m.d.comb += insn_jal.rvfi_mem_rdata.eq(self.rvfi_mem_rdata)
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m.d.comb += spec_insn_jal_valid.eq(insn_jal.spec_valid)
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m.d.comb += spec_insn_jal_trap.eq(insn_jal.spec_trap)
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m.d.comb += spec_insn_jal_rs1_addr.eq(insn_jal.spec_rs1_addr)
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m.d.comb += spec_insn_jal_rs2_addr.eq(insn_jal.spec_rs2_addr)
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m.d.comb += spec_insn_jal_rd_addr.eq(insn_jal.spec_rd_addr)
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m.d.comb += spec_insn_jal_rd_wdata.eq(insn_jal.spec_rd_wdata)
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m.d.comb += spec_insn_jal_pc_wdata.eq(insn_jal.spec_pc_wdata)
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m.d.comb += spec_insn_jal_mem_addr.eq(insn_jal.spec_mem_addr)
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m.d.comb += spec_insn_jal_mem_rmask.eq(insn_jal.spec_mem_rmask)
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m.d.comb += spec_insn_jal_mem_wmask.eq(insn_jal.spec_mem_wmask)
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m.d.comb += spec_insn_jal_mem_wdata.eq(insn_jal.spec_mem_wdata)
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spec_insn_jalr_valid = Signal(1)
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spec_insn_jalr_trap = Signal(1)
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spec_insn_jalr_rs1_addr = Signal(5)
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spec_insn_jalr_rs2_addr = Signal(5)
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spec_insn_jalr_rd_addr = Signal(5)
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spec_insn_jalr_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
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spec_insn_jalr_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
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spec_insn_jalr_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
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spec_insn_jalr_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
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spec_insn_jalr_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
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spec_insn_jalr_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
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m.submodules.insn_jalr = insn_jalr = rvfi_insn_jalr()
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m.d.comb += insn_jalr.rvfi_valid.eq(self.rvfi_valid)
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m.d.comb += insn_jalr.rvfi_insn.eq(self.rvfi_insn)
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m.d.comb += insn_jalr.rvfi_pc_rdata.eq(self.rvfi_pc_rdata)
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m.d.comb += insn_jalr.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata)
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m.d.comb += insn_jalr.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata)
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m.d.comb += insn_jalr.rvfi_mem_rdata.eq(self.rvfi_mem_rdata)
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m.d.comb += spec_insn_jalr_valid.eq(insn_jalr.spec_valid)
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m.d.comb += spec_insn_jalr_trap.eq(insn_jalr.spec_trap)
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m.d.comb += spec_insn_jalr_rs1_addr.eq(insn_jalr.spec_rs1_addr)
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m.d.comb += spec_insn_jalr_rs2_addr.eq(insn_jalr.spec_rs2_addr)
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m.d.comb += spec_insn_jalr_rd_addr.eq(insn_jalr.spec_rd_addr)
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m.d.comb += spec_insn_jalr_rd_wdata.eq(insn_jalr.spec_rd_wdata)
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m.d.comb += spec_insn_jalr_pc_wdata.eq(insn_jalr.spec_pc_wdata)
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m.d.comb += spec_insn_jalr_mem_addr.eq(insn_jalr.spec_mem_addr)
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m.d.comb += spec_insn_jalr_mem_rmask.eq(insn_jalr.spec_mem_rmask)
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m.d.comb += spec_insn_jalr_mem_wmask.eq(insn_jalr.spec_mem_wmask)
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m.d.comb += spec_insn_jalr_mem_wdata.eq(insn_jalr.spec_mem_wdata)
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spec_insn_beq_valid = Signal(1)
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spec_insn_beq_trap = Signal(1)
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spec_insn_beq_rs1_addr = Signal(5)
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spec_insn_beq_rs2_addr = Signal(5)
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spec_insn_beq_rd_addr = Signal(5)
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spec_insn_beq_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
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spec_insn_beq_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
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spec_insn_beq_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
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spec_insn_beq_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
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spec_insn_beq_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
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spec_insn_beq_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
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m.submodules.insn_beq = insn_beq = rvfi_insn_beq()
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m.d.comb += insn_beq.rvfi_valid.eq(self.rvfi_valid)
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m.d.comb += insn_beq.rvfi_insn.eq(self.rvfi_insn)
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m.d.comb += insn_beq.rvfi_pc_rdata.eq(self.rvfi_pc_rdata)
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m.d.comb += insn_beq.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata)
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m.d.comb += insn_beq.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata)
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m.d.comb += insn_beq.rvfi_mem_rdata.eq(self.rvfi_mem_rdata)
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m.d.comb += spec_insn_beq_valid.eq(insn_beq.spec_valid)
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m.d.comb += spec_insn_beq_trap.eq(insn_beq.spec_trap)
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|
|
m.d.comb += spec_insn_beq_rs1_addr.eq(insn_beq.spec_rs1_addr)
|
||
|
|
m.d.comb += spec_insn_beq_rs2_addr.eq(insn_beq.spec_rs2_addr)
|
||
|
|
m.d.comb += spec_insn_beq_rd_addr.eq(insn_beq.spec_rd_addr)
|
||
|
|
m.d.comb += spec_insn_beq_rd_wdata.eq(insn_beq.spec_rd_wdata)
|
||
|
|
m.d.comb += spec_insn_beq_pc_wdata.eq(insn_beq.spec_pc_wdata)
|
||
|
|
m.d.comb += spec_insn_beq_mem_addr.eq(insn_beq.spec_mem_addr)
|
||
|
|
m.d.comb += spec_insn_beq_mem_rmask.eq(insn_beq.spec_mem_rmask)
|
||
|
|
m.d.comb += spec_insn_beq_mem_wmask.eq(insn_beq.spec_mem_wmask)
|
||
|
|
m.d.comb += spec_insn_beq_mem_wdata.eq(insn_beq.spec_mem_wdata)
|
||
|
|
|
||
|
|
spec_insn_bne_valid = Signal(1)
|
||
|
|
spec_insn_bne_trap = Signal(1)
|
||
|
|
spec_insn_bne_rs1_addr = Signal(5)
|
||
|
|
spec_insn_bne_rs2_addr = Signal(5)
|
||
|
|
spec_insn_bne_rd_addr = Signal(5)
|
||
|
|
spec_insn_bne_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_bne_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_bne_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_bne_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
|
||
|
|
spec_insn_bne_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
|
||
|
|
spec_insn_bne_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
m.submodules.insn_bne = insn_bne = rvfi_insn_bne()
|
||
|
|
m.d.comb += insn_bne.rvfi_valid.eq(self.rvfi_valid)
|
||
|
|
m.d.comb += insn_bne.rvfi_insn.eq(self.rvfi_insn)
|
||
|
|
m.d.comb += insn_bne.rvfi_pc_rdata.eq(self.rvfi_pc_rdata)
|
||
|
|
m.d.comb += insn_bne.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata)
|
||
|
|
m.d.comb += insn_bne.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata)
|
||
|
|
m.d.comb += insn_bne.rvfi_mem_rdata.eq(self.rvfi_mem_rdata)
|
||
|
|
m.d.comb += spec_insn_bne_valid.eq(insn_bne.spec_valid)
|
||
|
|
m.d.comb += spec_insn_bne_trap.eq(insn_bne.spec_trap)
|
||
|
|
m.d.comb += spec_insn_bne_rs1_addr.eq(insn_bne.spec_rs1_addr)
|
||
|
|
m.d.comb += spec_insn_bne_rs2_addr.eq(insn_bne.spec_rs2_addr)
|
||
|
|
m.d.comb += spec_insn_bne_rd_addr.eq(insn_bne.spec_rd_addr)
|
||
|
|
m.d.comb += spec_insn_bne_rd_wdata.eq(insn_bne.spec_rd_wdata)
|
||
|
|
m.d.comb += spec_insn_bne_pc_wdata.eq(insn_bne.spec_pc_wdata)
|
||
|
|
m.d.comb += spec_insn_bne_mem_addr.eq(insn_bne.spec_mem_addr)
|
||
|
|
m.d.comb += spec_insn_bne_mem_rmask.eq(insn_bne.spec_mem_rmask)
|
||
|
|
m.d.comb += spec_insn_bne_mem_wmask.eq(insn_bne.spec_mem_wmask)
|
||
|
|
m.d.comb += spec_insn_bne_mem_wdata.eq(insn_bne.spec_mem_wdata)
|
||
|
|
|
||
|
|
spec_insn_blt_valid = Signal(1)
|
||
|
|
spec_insn_blt_trap = Signal(1)
|
||
|
|
spec_insn_blt_rs1_addr = Signal(5)
|
||
|
|
spec_insn_blt_rs2_addr = Signal(5)
|
||
|
|
spec_insn_blt_rd_addr = Signal(5)
|
||
|
|
spec_insn_blt_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_blt_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_blt_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_blt_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
|
||
|
|
spec_insn_blt_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
|
||
|
|
spec_insn_blt_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
m.submodules.insn_blt = insn_blt = rvfi_insn_blt()
|
||
|
|
m.d.comb += insn_blt.rvfi_valid.eq(self.rvfi_valid)
|
||
|
|
m.d.comb += insn_blt.rvfi_insn.eq(self.rvfi_insn)
|
||
|
|
m.d.comb += insn_blt.rvfi_pc_rdata.eq(self.rvfi_pc_rdata)
|
||
|
|
m.d.comb += insn_blt.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata)
|
||
|
|
m.d.comb += insn_blt.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata)
|
||
|
|
m.d.comb += insn_blt.rvfi_mem_rdata.eq(self.rvfi_mem_rdata)
|
||
|
|
m.d.comb += spec_insn_blt_valid.eq(insn_blt.spec_valid)
|
||
|
|
m.d.comb += spec_insn_blt_trap.eq(insn_blt.spec_trap)
|
||
|
|
m.d.comb += spec_insn_blt_rs1_addr.eq(insn_blt.spec_rs1_addr)
|
||
|
|
m.d.comb += spec_insn_blt_rs2_addr.eq(insn_blt.spec_rs2_addr)
|
||
|
|
m.d.comb += spec_insn_blt_rd_addr.eq(insn_blt.spec_rd_addr)
|
||
|
|
m.d.comb += spec_insn_blt_rd_wdata.eq(insn_blt.spec_rd_wdata)
|
||
|
|
m.d.comb += spec_insn_blt_pc_wdata.eq(insn_blt.spec_pc_wdata)
|
||
|
|
m.d.comb += spec_insn_blt_mem_addr.eq(insn_blt.spec_mem_addr)
|
||
|
|
m.d.comb += spec_insn_blt_mem_rmask.eq(insn_blt.spec_mem_rmask)
|
||
|
|
m.d.comb += spec_insn_blt_mem_wmask.eq(insn_blt.spec_mem_wmask)
|
||
|
|
m.d.comb += spec_insn_blt_mem_wdata.eq(insn_blt.spec_mem_wdata)
|
||
|
|
|
||
|
|
spec_insn_bge_valid = Signal(1)
|
||
|
|
spec_insn_bge_trap = Signal(1)
|
||
|
|
spec_insn_bge_rs1_addr = Signal(5)
|
||
|
|
spec_insn_bge_rs2_addr = Signal(5)
|
||
|
|
spec_insn_bge_rd_addr = Signal(5)
|
||
|
|
spec_insn_bge_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_bge_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_bge_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_bge_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
|
||
|
|
spec_insn_bge_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
|
||
|
|
spec_insn_bge_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
m.submodules.insn_bge = insn_bge = rvfi_insn_bge()
|
||
|
|
m.d.comb += insn_bge.rvfi_valid.eq(self.rvfi_valid)
|
||
|
|
m.d.comb += insn_bge.rvfi_insn.eq(self.rvfi_insn)
|
||
|
|
m.d.comb += insn_bge.rvfi_pc_rdata.eq(self.rvfi_pc_rdata)
|
||
|
|
m.d.comb += insn_bge.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata)
|
||
|
|
m.d.comb += insn_bge.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata)
|
||
|
|
m.d.comb += insn_bge.rvfi_mem_rdata.eq(self.rvfi_mem_rdata)
|
||
|
|
m.d.comb += spec_insn_bge_valid.eq(insn_bge.spec_valid)
|
||
|
|
m.d.comb += spec_insn_bge_trap.eq(insn_bge.spec_trap)
|
||
|
|
m.d.comb += spec_insn_bge_rs1_addr.eq(insn_bge.spec_rs1_addr)
|
||
|
|
m.d.comb += spec_insn_bge_rs2_addr.eq(insn_bge.spec_rs2_addr)
|
||
|
|
m.d.comb += spec_insn_bge_rd_addr.eq(insn_bge.spec_rd_addr)
|
||
|
|
m.d.comb += spec_insn_bge_rd_wdata.eq(insn_bge.spec_rd_wdata)
|
||
|
|
m.d.comb += spec_insn_bge_pc_wdata.eq(insn_bge.spec_pc_wdata)
|
||
|
|
m.d.comb += spec_insn_bge_mem_addr.eq(insn_bge.spec_mem_addr)
|
||
|
|
m.d.comb += spec_insn_bge_mem_rmask.eq(insn_bge.spec_mem_rmask)
|
||
|
|
m.d.comb += spec_insn_bge_mem_wmask.eq(insn_bge.spec_mem_wmask)
|
||
|
|
m.d.comb += spec_insn_bge_mem_wdata.eq(insn_bge.spec_mem_wdata)
|
||
|
|
|
||
|
|
spec_insn_bltu_valid = Signal(1)
|
||
|
|
spec_insn_bltu_trap = Signal(1)
|
||
|
|
spec_insn_bltu_rs1_addr = Signal(5)
|
||
|
|
spec_insn_bltu_rs2_addr = Signal(5)
|
||
|
|
spec_insn_bltu_rd_addr = Signal(5)
|
||
|
|
spec_insn_bltu_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_bltu_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_bltu_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_bltu_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
|
||
|
|
spec_insn_bltu_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
|
||
|
|
spec_insn_bltu_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
m.submodules.insn_bltu = insn_bltu = rvfi_insn_bltu()
|
||
|
|
m.d.comb += insn_bltu.rvfi_valid.eq(self.rvfi_valid)
|
||
|
|
m.d.comb += insn_bltu.rvfi_insn.eq(self.rvfi_insn)
|
||
|
|
m.d.comb += insn_bltu.rvfi_pc_rdata.eq(self.rvfi_pc_rdata)
|
||
|
|
m.d.comb += insn_bltu.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata)
|
||
|
|
m.d.comb += insn_bltu.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata)
|
||
|
|
m.d.comb += insn_bltu.rvfi_mem_rdata.eq(self.rvfi_mem_rdata)
|
||
|
|
m.d.comb += spec_insn_bltu_valid.eq(insn_bltu.spec_valid)
|
||
|
|
m.d.comb += spec_insn_bltu_trap.eq(insn_bltu.spec_trap)
|
||
|
|
m.d.comb += spec_insn_bltu_rs1_addr.eq(insn_bltu.spec_rs1_addr)
|
||
|
|
m.d.comb += spec_insn_bltu_rs2_addr.eq(insn_bltu.spec_rs2_addr)
|
||
|
|
m.d.comb += spec_insn_bltu_rd_addr.eq(insn_bltu.spec_rd_addr)
|
||
|
|
m.d.comb += spec_insn_bltu_rd_wdata.eq(insn_bltu.spec_rd_wdata)
|
||
|
|
m.d.comb += spec_insn_bltu_pc_wdata.eq(insn_bltu.spec_pc_wdata)
|
||
|
|
m.d.comb += spec_insn_bltu_mem_addr.eq(insn_bltu.spec_mem_addr)
|
||
|
|
m.d.comb += spec_insn_bltu_mem_rmask.eq(insn_bltu.spec_mem_rmask)
|
||
|
|
m.d.comb += spec_insn_bltu_mem_wmask.eq(insn_bltu.spec_mem_wmask)
|
||
|
|
m.d.comb += spec_insn_bltu_mem_wdata.eq(insn_bltu.spec_mem_wdata)
|
||
|
|
|
||
|
|
spec_insn_bgeu_valid = Signal(1)
|
||
|
|
spec_insn_bgeu_trap = Signal(1)
|
||
|
|
spec_insn_bgeu_rs1_addr = Signal(5)
|
||
|
|
spec_insn_bgeu_rs2_addr = Signal(5)
|
||
|
|
spec_insn_bgeu_rd_addr = Signal(5)
|
||
|
|
spec_insn_bgeu_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_bgeu_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_bgeu_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_bgeu_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
|
||
|
|
spec_insn_bgeu_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
|
||
|
|
spec_insn_bgeu_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
m.submodules.insn_bgeu = insn_bgeu = rvfi_insn_bgeu()
|
||
|
|
m.d.comb += insn_bgeu.rvfi_valid.eq(self.rvfi_valid)
|
||
|
|
m.d.comb += insn_bgeu.rvfi_insn.eq(self.rvfi_insn)
|
||
|
|
m.d.comb += insn_bgeu.rvfi_pc_rdata.eq(self.rvfi_pc_rdata)
|
||
|
|
m.d.comb += insn_bgeu.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata)
|
||
|
|
m.d.comb += insn_bgeu.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata)
|
||
|
|
m.d.comb += insn_bgeu.rvfi_mem_rdata.eq(self.rvfi_mem_rdata)
|
||
|
|
m.d.comb += spec_insn_bgeu_valid.eq(insn_bgeu.spec_valid)
|
||
|
|
m.d.comb += spec_insn_bgeu_trap.eq(insn_bgeu.spec_trap)
|
||
|
|
m.d.comb += spec_insn_bgeu_rs1_addr.eq(insn_bgeu.spec_rs1_addr)
|
||
|
|
m.d.comb += spec_insn_bgeu_rs2_addr.eq(insn_bgeu.spec_rs2_addr)
|
||
|
|
m.d.comb += spec_insn_bgeu_rd_addr.eq(insn_bgeu.spec_rd_addr)
|
||
|
|
m.d.comb += spec_insn_bgeu_rd_wdata.eq(insn_bgeu.spec_rd_wdata)
|
||
|
|
m.d.comb += spec_insn_bgeu_pc_wdata.eq(insn_bgeu.spec_pc_wdata)
|
||
|
|
m.d.comb += spec_insn_bgeu_mem_addr.eq(insn_bgeu.spec_mem_addr)
|
||
|
|
m.d.comb += spec_insn_bgeu_mem_rmask.eq(insn_bgeu.spec_mem_rmask)
|
||
|
|
m.d.comb += spec_insn_bgeu_mem_wmask.eq(insn_bgeu.spec_mem_wmask)
|
||
|
|
m.d.comb += spec_insn_bgeu_mem_wdata.eq(insn_bgeu.spec_mem_wdata)
|
||
|
|
|
||
|
|
spec_insn_lb_valid = Signal(1)
|
||
|
|
spec_insn_lb_trap = Signal(1)
|
||
|
|
spec_insn_lb_rs1_addr = Signal(5)
|
||
|
|
spec_insn_lb_rs2_addr = Signal(5)
|
||
|
|
spec_insn_lb_rd_addr = Signal(5)
|
||
|
|
spec_insn_lb_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_lb_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_lb_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_lb_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
|
||
|
|
spec_insn_lb_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
|
||
|
|
spec_insn_lb_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
m.submodules.insn_lb = insn_lb = rvfi_insn_lb()
|
||
|
|
m.d.comb += insn_lb.rvfi_valid.eq(self.rvfi_valid)
|
||
|
|
m.d.comb += insn_lb.rvfi_insn.eq(self.rvfi_insn)
|
||
|
|
m.d.comb += insn_lb.rvfi_pc_rdata.eq(self.rvfi_pc_rdata)
|
||
|
|
m.d.comb += insn_lb.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata)
|
||
|
|
m.d.comb += insn_lb.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata)
|
||
|
|
m.d.comb += insn_lb.rvfi_mem_rdata.eq(self.rvfi_mem_rdata)
|
||
|
|
m.d.comb += spec_insn_lb_valid.eq(insn_lb.spec_valid)
|
||
|
|
m.d.comb += spec_insn_lb_trap.eq(insn_lb.spec_trap)
|
||
|
|
m.d.comb += spec_insn_lb_rs1_addr.eq(insn_lb.spec_rs1_addr)
|
||
|
|
m.d.comb += spec_insn_lb_rs2_addr.eq(insn_lb.spec_rs2_addr)
|
||
|
|
m.d.comb += spec_insn_lb_rd_addr.eq(insn_lb.spec_rd_addr)
|
||
|
|
m.d.comb += spec_insn_lb_rd_wdata.eq(insn_lb.spec_rd_wdata)
|
||
|
|
m.d.comb += spec_insn_lb_pc_wdata.eq(insn_lb.spec_pc_wdata)
|
||
|
|
m.d.comb += spec_insn_lb_mem_addr.eq(insn_lb.spec_mem_addr)
|
||
|
|
m.d.comb += spec_insn_lb_mem_rmask.eq(insn_lb.spec_mem_rmask)
|
||
|
|
m.d.comb += spec_insn_lb_mem_wmask.eq(insn_lb.spec_mem_wmask)
|
||
|
|
m.d.comb += spec_insn_lb_mem_wdata.eq(insn_lb.spec_mem_wdata)
|
||
|
|
|
||
|
|
spec_insn_lh_valid = Signal(1)
|
||
|
|
spec_insn_lh_trap = Signal(1)
|
||
|
|
spec_insn_lh_rs1_addr = Signal(5)
|
||
|
|
spec_insn_lh_rs2_addr = Signal(5)
|
||
|
|
spec_insn_lh_rd_addr = Signal(5)
|
||
|
|
spec_insn_lh_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_lh_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_lh_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_lh_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
|
||
|
|
spec_insn_lh_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
|
||
|
|
spec_insn_lh_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
m.submodules.insn_lh = insn_lh = rvfi_insn_lh()
|
||
|
|
m.d.comb += insn_lh.rvfi_valid.eq(self.rvfi_valid)
|
||
|
|
m.d.comb += insn_lh.rvfi_insn.eq(self.rvfi_insn)
|
||
|
|
m.d.comb += insn_lh.rvfi_pc_rdata.eq(self.rvfi_pc_rdata)
|
||
|
|
m.d.comb += insn_lh.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata)
|
||
|
|
m.d.comb += insn_lh.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata)
|
||
|
|
m.d.comb += insn_lh.rvfi_mem_rdata.eq(self.rvfi_mem_rdata)
|
||
|
|
m.d.comb += spec_insn_lh_valid.eq(insn_lh.spec_valid)
|
||
|
|
m.d.comb += spec_insn_lh_trap.eq(insn_lh.spec_trap)
|
||
|
|
m.d.comb += spec_insn_lh_rs1_addr.eq(insn_lh.spec_rs1_addr)
|
||
|
|
m.d.comb += spec_insn_lh_rs2_addr.eq(insn_lh.spec_rs2_addr)
|
||
|
|
m.d.comb += spec_insn_lh_rd_addr.eq(insn_lh.spec_rd_addr)
|
||
|
|
m.d.comb += spec_insn_lh_rd_wdata.eq(insn_lh.spec_rd_wdata)
|
||
|
|
m.d.comb += spec_insn_lh_pc_wdata.eq(insn_lh.spec_pc_wdata)
|
||
|
|
m.d.comb += spec_insn_lh_mem_addr.eq(insn_lh.spec_mem_addr)
|
||
|
|
m.d.comb += spec_insn_lh_mem_rmask.eq(insn_lh.spec_mem_rmask)
|
||
|
|
m.d.comb += spec_insn_lh_mem_wmask.eq(insn_lh.spec_mem_wmask)
|
||
|
|
m.d.comb += spec_insn_lh_mem_wdata.eq(insn_lh.spec_mem_wdata)
|
||
|
|
|
||
|
|
spec_insn_lw_valid = Signal(1)
|
||
|
|
spec_insn_lw_trap = Signal(1)
|
||
|
|
spec_insn_lw_rs1_addr = Signal(5)
|
||
|
|
spec_insn_lw_rs2_addr = Signal(5)
|
||
|
|
spec_insn_lw_rd_addr = Signal(5)
|
||
|
|
spec_insn_lw_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_lw_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_lw_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_lw_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
|
||
|
|
spec_insn_lw_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
|
||
|
|
spec_insn_lw_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
m.submodules.insn_lw = insn_lw = rvfi_insn_lw()
|
||
|
|
m.d.comb += insn_lw.rvfi_valid.eq(self.rvfi_valid)
|
||
|
|
m.d.comb += insn_lw.rvfi_insn.eq(self.rvfi_insn)
|
||
|
|
m.d.comb += insn_lw.rvfi_pc_rdata.eq(self.rvfi_pc_rdata)
|
||
|
|
m.d.comb += insn_lw.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata)
|
||
|
|
m.d.comb += insn_lw.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata)
|
||
|
|
m.d.comb += insn_lw.rvfi_mem_rdata.eq(self.rvfi_mem_rdata)
|
||
|
|
m.d.comb += spec_insn_lw_valid.eq(insn_lw.spec_valid)
|
||
|
|
m.d.comb += spec_insn_lw_trap.eq(insn_lw.spec_trap)
|
||
|
|
m.d.comb += spec_insn_lw_rs1_addr.eq(insn_lw.spec_rs1_addr)
|
||
|
|
m.d.comb += spec_insn_lw_rs2_addr.eq(insn_lw.spec_rs2_addr)
|
||
|
|
m.d.comb += spec_insn_lw_rd_addr.eq(insn_lw.spec_rd_addr)
|
||
|
|
m.d.comb += spec_insn_lw_rd_wdata.eq(insn_lw.spec_rd_wdata)
|
||
|
|
m.d.comb += spec_insn_lw_pc_wdata.eq(insn_lw.spec_pc_wdata)
|
||
|
|
m.d.comb += spec_insn_lw_mem_addr.eq(insn_lw.spec_mem_addr)
|
||
|
|
m.d.comb += spec_insn_lw_mem_rmask.eq(insn_lw.spec_mem_rmask)
|
||
|
|
m.d.comb += spec_insn_lw_mem_wmask.eq(insn_lw.spec_mem_wmask)
|
||
|
|
m.d.comb += spec_insn_lw_mem_wdata.eq(insn_lw.spec_mem_wdata)
|
||
|
|
|
||
|
|
spec_insn_lbu_valid = Signal(1)
|
||
|
|
spec_insn_lbu_trap = Signal(1)
|
||
|
|
spec_insn_lbu_rs1_addr = Signal(5)
|
||
|
|
spec_insn_lbu_rs2_addr = Signal(5)
|
||
|
|
spec_insn_lbu_rd_addr = Signal(5)
|
||
|
|
spec_insn_lbu_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_lbu_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_lbu_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_lbu_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
|
||
|
|
spec_insn_lbu_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
|
||
|
|
spec_insn_lbu_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
m.submodules.insn_lbu = insn_lbu = rvfi_insn_lbu()
|
||
|
|
m.d.comb += insn_lbu.rvfi_valid.eq(self.rvfi_valid)
|
||
|
|
m.d.comb += insn_lbu.rvfi_insn.eq(self.rvfi_insn)
|
||
|
|
m.d.comb += insn_lbu.rvfi_pc_rdata.eq(self.rvfi_pc_rdata)
|
||
|
|
m.d.comb += insn_lbu.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata)
|
||
|
|
m.d.comb += insn_lbu.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata)
|
||
|
|
m.d.comb += insn_lbu.rvfi_mem_rdata.eq(self.rvfi_mem_rdata)
|
||
|
|
m.d.comb += spec_insn_lbu_valid.eq(insn_lbu.spec_valid)
|
||
|
|
m.d.comb += spec_insn_lbu_trap.eq(insn_lbu.spec_trap)
|
||
|
|
m.d.comb += spec_insn_lbu_rs1_addr.eq(insn_lbu.spec_rs1_addr)
|
||
|
|
m.d.comb += spec_insn_lbu_rs2_addr.eq(insn_lbu.spec_rs2_addr)
|
||
|
|
m.d.comb += spec_insn_lbu_rd_addr.eq(insn_lbu.spec_rd_addr)
|
||
|
|
m.d.comb += spec_insn_lbu_rd_wdata.eq(insn_lbu.spec_rd_wdata)
|
||
|
|
m.d.comb += spec_insn_lbu_pc_wdata.eq(insn_lbu.spec_pc_wdata)
|
||
|
|
m.d.comb += spec_insn_lbu_mem_addr.eq(insn_lbu.spec_mem_addr)
|
||
|
|
m.d.comb += spec_insn_lbu_mem_rmask.eq(insn_lbu.spec_mem_rmask)
|
||
|
|
m.d.comb += spec_insn_lbu_mem_wmask.eq(insn_lbu.spec_mem_wmask)
|
||
|
|
m.d.comb += spec_insn_lbu_mem_wdata.eq(insn_lbu.spec_mem_wdata)
|
||
|
|
|
||
|
|
spec_insn_lhu_valid = Signal(1)
|
||
|
|
spec_insn_lhu_trap = Signal(1)
|
||
|
|
spec_insn_lhu_rs1_addr = Signal(5)
|
||
|
|
spec_insn_lhu_rs2_addr = Signal(5)
|
||
|
|
spec_insn_lhu_rd_addr = Signal(5)
|
||
|
|
spec_insn_lhu_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_lhu_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_lhu_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_lhu_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
|
||
|
|
spec_insn_lhu_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
|
||
|
|
spec_insn_lhu_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
m.submodules.insn_lhu = insn_lhu = rvfi_insn_lhu()
|
||
|
|
m.d.comb += insn_lhu.rvfi_valid.eq(self.rvfi_valid)
|
||
|
|
m.d.comb += insn_lhu.rvfi_insn.eq(self.rvfi_insn)
|
||
|
|
m.d.comb += insn_lhu.rvfi_pc_rdata.eq(self.rvfi_pc_rdata)
|
||
|
|
m.d.comb += insn_lhu.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata)
|
||
|
|
m.d.comb += insn_lhu.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata)
|
||
|
|
m.d.comb += insn_lhu.rvfi_mem_rdata.eq(self.rvfi_mem_rdata)
|
||
|
|
m.d.comb += spec_insn_lhu_valid.eq(insn_lhu.spec_valid)
|
||
|
|
m.d.comb += spec_insn_lhu_trap.eq(insn_lhu.spec_trap)
|
||
|
|
m.d.comb += spec_insn_lhu_rs1_addr.eq(insn_lhu.spec_rs1_addr)
|
||
|
|
m.d.comb += spec_insn_lhu_rs2_addr.eq(insn_lhu.spec_rs2_addr)
|
||
|
|
m.d.comb += spec_insn_lhu_rd_addr.eq(insn_lhu.spec_rd_addr)
|
||
|
|
m.d.comb += spec_insn_lhu_rd_wdata.eq(insn_lhu.spec_rd_wdata)
|
||
|
|
m.d.comb += spec_insn_lhu_pc_wdata.eq(insn_lhu.spec_pc_wdata)
|
||
|
|
m.d.comb += spec_insn_lhu_mem_addr.eq(insn_lhu.spec_mem_addr)
|
||
|
|
m.d.comb += spec_insn_lhu_mem_rmask.eq(insn_lhu.spec_mem_rmask)
|
||
|
|
m.d.comb += spec_insn_lhu_mem_wmask.eq(insn_lhu.spec_mem_wmask)
|
||
|
|
m.d.comb += spec_insn_lhu_mem_wdata.eq(insn_lhu.spec_mem_wdata)
|
||
|
|
|
||
|
|
spec_insn_sb_valid = Signal(1)
|
||
|
|
spec_insn_sb_trap = Signal(1)
|
||
|
|
spec_insn_sb_rs1_addr = Signal(5)
|
||
|
|
spec_insn_sb_rs2_addr = Signal(5)
|
||
|
|
spec_insn_sb_rd_addr = Signal(5)
|
||
|
|
spec_insn_sb_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_sb_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_sb_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_sb_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
|
||
|
|
spec_insn_sb_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
|
||
|
|
spec_insn_sb_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
m.submodules.insn_sb = insn_sb = rvfi_insn_sb()
|
||
|
|
m.d.comb += insn_sb.rvfi_valid.eq(self.rvfi_valid)
|
||
|
|
m.d.comb += insn_sb.rvfi_insn.eq(self.rvfi_insn)
|
||
|
|
m.d.comb += insn_sb.rvfi_pc_rdata.eq(self.rvfi_pc_rdata)
|
||
|
|
m.d.comb += insn_sb.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata)
|
||
|
|
m.d.comb += insn_sb.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata)
|
||
|
|
m.d.comb += insn_sb.rvfi_mem_rdata.eq(self.rvfi_mem_rdata)
|
||
|
|
m.d.comb += spec_insn_sb_valid.eq(insn_sb.spec_valid)
|
||
|
|
m.d.comb += spec_insn_sb_trap.eq(insn_sb.spec_trap)
|
||
|
|
m.d.comb += spec_insn_sb_rs1_addr.eq(insn_sb.spec_rs1_addr)
|
||
|
|
m.d.comb += spec_insn_sb_rs2_addr.eq(insn_sb.spec_rs2_addr)
|
||
|
|
m.d.comb += spec_insn_sb_rd_addr.eq(insn_sb.spec_rd_addr)
|
||
|
|
m.d.comb += spec_insn_sb_rd_wdata.eq(insn_sb.spec_rd_wdata)
|
||
|
|
m.d.comb += spec_insn_sb_pc_wdata.eq(insn_sb.spec_pc_wdata)
|
||
|
|
m.d.comb += spec_insn_sb_mem_addr.eq(insn_sb.spec_mem_addr)
|
||
|
|
m.d.comb += spec_insn_sb_mem_rmask.eq(insn_sb.spec_mem_rmask)
|
||
|
|
m.d.comb += spec_insn_sb_mem_wmask.eq(insn_sb.spec_mem_wmask)
|
||
|
|
m.d.comb += spec_insn_sb_mem_wdata.eq(insn_sb.spec_mem_wdata)
|
||
|
|
|
||
|
|
spec_insn_sh_valid = Signal(1)
|
||
|
|
spec_insn_sh_trap = Signal(1)
|
||
|
|
spec_insn_sh_rs1_addr = Signal(5)
|
||
|
|
spec_insn_sh_rs2_addr = Signal(5)
|
||
|
|
spec_insn_sh_rd_addr = Signal(5)
|
||
|
|
spec_insn_sh_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_sh_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_sh_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_sh_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
|
||
|
|
spec_insn_sh_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
|
||
|
|
spec_insn_sh_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
m.submodules.insn_sh = insn_sh = rvfi_insn_sh()
|
||
|
|
m.d.comb += insn_sh.rvfi_valid.eq(self.rvfi_valid)
|
||
|
|
m.d.comb += insn_sh.rvfi_insn.eq(self.rvfi_insn)
|
||
|
|
m.d.comb += insn_sh.rvfi_pc_rdata.eq(self.rvfi_pc_rdata)
|
||
|
|
m.d.comb += insn_sh.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata)
|
||
|
|
m.d.comb += insn_sh.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata)
|
||
|
|
m.d.comb += insn_sh.rvfi_mem_rdata.eq(self.rvfi_mem_rdata)
|
||
|
|
m.d.comb += spec_insn_sh_valid.eq(insn_sh.spec_valid)
|
||
|
|
m.d.comb += spec_insn_sh_trap.eq(insn_sh.spec_trap)
|
||
|
|
m.d.comb += spec_insn_sh_rs1_addr.eq(insn_sh.spec_rs1_addr)
|
||
|
|
m.d.comb += spec_insn_sh_rs2_addr.eq(insn_sh.spec_rs2_addr)
|
||
|
|
m.d.comb += spec_insn_sh_rd_addr.eq(insn_sh.spec_rd_addr)
|
||
|
|
m.d.comb += spec_insn_sh_rd_wdata.eq(insn_sh.spec_rd_wdata)
|
||
|
|
m.d.comb += spec_insn_sh_pc_wdata.eq(insn_sh.spec_pc_wdata)
|
||
|
|
m.d.comb += spec_insn_sh_mem_addr.eq(insn_sh.spec_mem_addr)
|
||
|
|
m.d.comb += spec_insn_sh_mem_rmask.eq(insn_sh.spec_mem_rmask)
|
||
|
|
m.d.comb += spec_insn_sh_mem_wmask.eq(insn_sh.spec_mem_wmask)
|
||
|
|
m.d.comb += spec_insn_sh_mem_wdata.eq(insn_sh.spec_mem_wdata)
|
||
|
|
|
||
|
|
spec_insn_sw_valid = Signal(1)
|
||
|
|
spec_insn_sw_trap = Signal(1)
|
||
|
|
spec_insn_sw_rs1_addr = Signal(5)
|
||
|
|
spec_insn_sw_rs2_addr = Signal(5)
|
||
|
|
spec_insn_sw_rd_addr = Signal(5)
|
||
|
|
spec_insn_sw_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_sw_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_sw_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_sw_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
|
||
|
|
spec_insn_sw_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
|
||
|
|
spec_insn_sw_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
m.submodules.insn_sw = insn_sw = rvfi_insn_sw()
|
||
|
|
m.d.comb += insn_sw.rvfi_valid.eq(self.rvfi_valid)
|
||
|
|
m.d.comb += insn_sw.rvfi_insn.eq(self.rvfi_insn)
|
||
|
|
m.d.comb += insn_sw.rvfi_pc_rdata.eq(self.rvfi_pc_rdata)
|
||
|
|
m.d.comb += insn_sw.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata)
|
||
|
|
m.d.comb += insn_sw.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata)
|
||
|
|
m.d.comb += insn_sw.rvfi_mem_rdata.eq(self.rvfi_mem_rdata)
|
||
|
|
m.d.comb += spec_insn_sw_valid.eq(insn_sw.spec_valid)
|
||
|
|
m.d.comb += spec_insn_sw_trap.eq(insn_sw.spec_trap)
|
||
|
|
m.d.comb += spec_insn_sw_rs1_addr.eq(insn_sw.spec_rs1_addr)
|
||
|
|
m.d.comb += spec_insn_sw_rs2_addr.eq(insn_sw.spec_rs2_addr)
|
||
|
|
m.d.comb += spec_insn_sw_rd_addr.eq(insn_sw.spec_rd_addr)
|
||
|
|
m.d.comb += spec_insn_sw_rd_wdata.eq(insn_sw.spec_rd_wdata)
|
||
|
|
m.d.comb += spec_insn_sw_pc_wdata.eq(insn_sw.spec_pc_wdata)
|
||
|
|
m.d.comb += spec_insn_sw_mem_addr.eq(insn_sw.spec_mem_addr)
|
||
|
|
m.d.comb += spec_insn_sw_mem_rmask.eq(insn_sw.spec_mem_rmask)
|
||
|
|
m.d.comb += spec_insn_sw_mem_wmask.eq(insn_sw.spec_mem_wmask)
|
||
|
|
m.d.comb += spec_insn_sw_mem_wdata.eq(insn_sw.spec_mem_wdata)
|
||
|
|
|
||
|
|
spec_insn_addi_valid = Signal(1)
|
||
|
|
spec_insn_addi_trap = Signal(1)
|
||
|
|
spec_insn_addi_rs1_addr = Signal(5)
|
||
|
|
spec_insn_addi_rs2_addr = Signal(5)
|
||
|
|
spec_insn_addi_rd_addr = Signal(5)
|
||
|
|
spec_insn_addi_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_addi_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_addi_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_addi_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
|
||
|
|
spec_insn_addi_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
|
||
|
|
spec_insn_addi_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
m.submodules.insn_addi = insn_addi = rvfi_insn_addi()
|
||
|
|
m.d.comb += insn_addi.rvfi_valid.eq(self.rvfi_valid)
|
||
|
|
m.d.comb += insn_addi.rvfi_insn.eq(self.rvfi_insn)
|
||
|
|
m.d.comb += insn_addi.rvfi_pc_rdata.eq(self.rvfi_pc_rdata)
|
||
|
|
m.d.comb += insn_addi.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata)
|
||
|
|
m.d.comb += insn_addi.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata)
|
||
|
|
m.d.comb += insn_addi.rvfi_mem_rdata.eq(self.rvfi_mem_rdata)
|
||
|
|
m.d.comb += spec_insn_addi_valid.eq(insn_addi.spec_valid)
|
||
|
|
m.d.comb += spec_insn_addi_trap.eq(insn_addi.spec_trap)
|
||
|
|
m.d.comb += spec_insn_addi_rs1_addr.eq(insn_addi.spec_rs1_addr)
|
||
|
|
m.d.comb += spec_insn_addi_rs2_addr.eq(insn_addi.spec_rs2_addr)
|
||
|
|
m.d.comb += spec_insn_addi_rd_addr.eq(insn_addi.spec_rd_addr)
|
||
|
|
m.d.comb += spec_insn_addi_rd_wdata.eq(insn_addi.spec_rd_wdata)
|
||
|
|
m.d.comb += spec_insn_addi_pc_wdata.eq(insn_addi.spec_pc_wdata)
|
||
|
|
m.d.comb += spec_insn_addi_mem_addr.eq(insn_addi.spec_mem_addr)
|
||
|
|
m.d.comb += spec_insn_addi_mem_rmask.eq(insn_addi.spec_mem_rmask)
|
||
|
|
m.d.comb += spec_insn_addi_mem_wmask.eq(insn_addi.spec_mem_wmask)
|
||
|
|
m.d.comb += spec_insn_addi_mem_wdata.eq(insn_addi.spec_mem_wdata)
|
||
|
|
|
||
|
|
spec_insn_slti_valid = Signal(1)
|
||
|
|
spec_insn_slti_trap = Signal(1)
|
||
|
|
spec_insn_slti_rs1_addr = Signal(5)
|
||
|
|
spec_insn_slti_rs2_addr = Signal(5)
|
||
|
|
spec_insn_slti_rd_addr = Signal(5)
|
||
|
|
spec_insn_slti_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_slti_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_slti_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_slti_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
|
||
|
|
spec_insn_slti_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
|
||
|
|
spec_insn_slti_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
m.submodules.insn_slti = insn_slti = rvfi_insn_slti()
|
||
|
|
m.d.comb += insn_slti.rvfi_valid.eq(self.rvfi_valid)
|
||
|
|
m.d.comb += insn_slti.rvfi_insn.eq(self.rvfi_insn)
|
||
|
|
m.d.comb += insn_slti.rvfi_pc_rdata.eq(self.rvfi_pc_rdata)
|
||
|
|
m.d.comb += insn_slti.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata)
|
||
|
|
m.d.comb += insn_slti.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata)
|
||
|
|
m.d.comb += insn_slti.rvfi_mem_rdata.eq(self.rvfi_mem_rdata)
|
||
|
|
m.d.comb += spec_insn_slti_valid.eq(insn_slti.spec_valid)
|
||
|
|
m.d.comb += spec_insn_slti_trap.eq(insn_slti.spec_trap)
|
||
|
|
m.d.comb += spec_insn_slti_rs1_addr.eq(insn_slti.spec_rs1_addr)
|
||
|
|
m.d.comb += spec_insn_slti_rs2_addr.eq(insn_slti.spec_rs2_addr)
|
||
|
|
m.d.comb += spec_insn_slti_rd_addr.eq(insn_slti.spec_rd_addr)
|
||
|
|
m.d.comb += spec_insn_slti_rd_wdata.eq(insn_slti.spec_rd_wdata)
|
||
|
|
m.d.comb += spec_insn_slti_pc_wdata.eq(insn_slti.spec_pc_wdata)
|
||
|
|
m.d.comb += spec_insn_slti_mem_addr.eq(insn_slti.spec_mem_addr)
|
||
|
|
m.d.comb += spec_insn_slti_mem_rmask.eq(insn_slti.spec_mem_rmask)
|
||
|
|
m.d.comb += spec_insn_slti_mem_wmask.eq(insn_slti.spec_mem_wmask)
|
||
|
|
m.d.comb += spec_insn_slti_mem_wdata.eq(insn_slti.spec_mem_wdata)
|
||
|
|
|
||
|
|
spec_insn_sltiu_valid = Signal(1)
|
||
|
|
spec_insn_sltiu_trap = Signal(1)
|
||
|
|
spec_insn_sltiu_rs1_addr = Signal(5)
|
||
|
|
spec_insn_sltiu_rs2_addr = Signal(5)
|
||
|
|
spec_insn_sltiu_rd_addr = Signal(5)
|
||
|
|
spec_insn_sltiu_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_sltiu_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_sltiu_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_sltiu_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
|
||
|
|
spec_insn_sltiu_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
|
||
|
|
spec_insn_sltiu_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
m.submodules.insn_sltiu = insn_sltiu = rvfi_insn_sltiu()
|
||
|
|
m.d.comb += insn_sltiu.rvfi_valid.eq(self.rvfi_valid)
|
||
|
|
m.d.comb += insn_sltiu.rvfi_insn.eq(self.rvfi_insn)
|
||
|
|
m.d.comb += insn_sltiu.rvfi_pc_rdata.eq(self.rvfi_pc_rdata)
|
||
|
|
m.d.comb += insn_sltiu.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata)
|
||
|
|
m.d.comb += insn_sltiu.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata)
|
||
|
|
m.d.comb += insn_sltiu.rvfi_mem_rdata.eq(self.rvfi_mem_rdata)
|
||
|
|
m.d.comb += spec_insn_sltiu_valid.eq(insn_sltiu.spec_valid)
|
||
|
|
m.d.comb += spec_insn_sltiu_trap.eq(insn_sltiu.spec_trap)
|
||
|
|
m.d.comb += spec_insn_sltiu_rs1_addr.eq(insn_sltiu.spec_rs1_addr)
|
||
|
|
m.d.comb += spec_insn_sltiu_rs2_addr.eq(insn_sltiu.spec_rs2_addr)
|
||
|
|
m.d.comb += spec_insn_sltiu_rd_addr.eq(insn_sltiu.spec_rd_addr)
|
||
|
|
m.d.comb += spec_insn_sltiu_rd_wdata.eq(insn_sltiu.spec_rd_wdata)
|
||
|
|
m.d.comb += spec_insn_sltiu_pc_wdata.eq(insn_sltiu.spec_pc_wdata)
|
||
|
|
m.d.comb += spec_insn_sltiu_mem_addr.eq(insn_sltiu.spec_mem_addr)
|
||
|
|
m.d.comb += spec_insn_sltiu_mem_rmask.eq(insn_sltiu.spec_mem_rmask)
|
||
|
|
m.d.comb += spec_insn_sltiu_mem_wmask.eq(insn_sltiu.spec_mem_wmask)
|
||
|
|
m.d.comb += spec_insn_sltiu_mem_wdata.eq(insn_sltiu.spec_mem_wdata)
|
||
|
|
|
||
|
|
spec_insn_xori_valid = Signal(1)
|
||
|
|
spec_insn_xori_trap = Signal(1)
|
||
|
|
spec_insn_xori_rs1_addr = Signal(5)
|
||
|
|
spec_insn_xori_rs2_addr = Signal(5)
|
||
|
|
spec_insn_xori_rd_addr = Signal(5)
|
||
|
|
spec_insn_xori_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_xori_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_xori_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_xori_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
|
||
|
|
spec_insn_xori_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
|
||
|
|
spec_insn_xori_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
m.submodules.insn_xori = insn_xori = rvfi_insn_xori()
|
||
|
|
m.d.comb += insn_xori.rvfi_valid.eq(self.rvfi_valid)
|
||
|
|
m.d.comb += insn_xori.rvfi_insn.eq(self.rvfi_insn)
|
||
|
|
m.d.comb += insn_xori.rvfi_pc_rdata.eq(self.rvfi_pc_rdata)
|
||
|
|
m.d.comb += insn_xori.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata)
|
||
|
|
m.d.comb += insn_xori.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata)
|
||
|
|
m.d.comb += insn_xori.rvfi_mem_rdata.eq(self.rvfi_mem_rdata)
|
||
|
|
m.d.comb += spec_insn_xori_valid.eq(insn_xori.spec_valid)
|
||
|
|
m.d.comb += spec_insn_xori_trap.eq(insn_xori.spec_trap)
|
||
|
|
m.d.comb += spec_insn_xori_rs1_addr.eq(insn_xori.spec_rs1_addr)
|
||
|
|
m.d.comb += spec_insn_xori_rs2_addr.eq(insn_xori.spec_rs2_addr)
|
||
|
|
m.d.comb += spec_insn_xori_rd_addr.eq(insn_xori.spec_rd_addr)
|
||
|
|
m.d.comb += spec_insn_xori_rd_wdata.eq(insn_xori.spec_rd_wdata)
|
||
|
|
m.d.comb += spec_insn_xori_pc_wdata.eq(insn_xori.spec_pc_wdata)
|
||
|
|
m.d.comb += spec_insn_xori_mem_addr.eq(insn_xori.spec_mem_addr)
|
||
|
|
m.d.comb += spec_insn_xori_mem_rmask.eq(insn_xori.spec_mem_rmask)
|
||
|
|
m.d.comb += spec_insn_xori_mem_wmask.eq(insn_xori.spec_mem_wmask)
|
||
|
|
m.d.comb += spec_insn_xori_mem_wdata.eq(insn_xori.spec_mem_wdata)
|
||
|
|
|
||
|
|
spec_insn_ori_valid = Signal(1)
|
||
|
|
spec_insn_ori_trap = Signal(1)
|
||
|
|
spec_insn_ori_rs1_addr = Signal(5)
|
||
|
|
spec_insn_ori_rs2_addr = Signal(5)
|
||
|
|
spec_insn_ori_rd_addr = Signal(5)
|
||
|
|
spec_insn_ori_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_ori_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_ori_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_ori_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
|
||
|
|
spec_insn_ori_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
|
||
|
|
spec_insn_ori_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
m.submodules.insn_ori = insn_ori = rvfi_insn_ori()
|
||
|
|
m.d.comb += insn_ori.rvfi_valid.eq(self.rvfi_valid)
|
||
|
|
m.d.comb += insn_ori.rvfi_insn.eq(self.rvfi_insn)
|
||
|
|
m.d.comb += insn_ori.rvfi_pc_rdata.eq(self.rvfi_pc_rdata)
|
||
|
|
m.d.comb += insn_ori.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata)
|
||
|
|
m.d.comb += insn_ori.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata)
|
||
|
|
m.d.comb += insn_ori.rvfi_mem_rdata.eq(self.rvfi_mem_rdata)
|
||
|
|
m.d.comb += spec_insn_ori_valid.eq(insn_ori.spec_valid)
|
||
|
|
m.d.comb += spec_insn_ori_trap.eq(insn_ori.spec_trap)
|
||
|
|
m.d.comb += spec_insn_ori_rs1_addr.eq(insn_ori.spec_rs1_addr)
|
||
|
|
m.d.comb += spec_insn_ori_rs2_addr.eq(insn_ori.spec_rs2_addr)
|
||
|
|
m.d.comb += spec_insn_ori_rd_addr.eq(insn_ori.spec_rd_addr)
|
||
|
|
m.d.comb += spec_insn_ori_rd_wdata.eq(insn_ori.spec_rd_wdata)
|
||
|
|
m.d.comb += spec_insn_ori_pc_wdata.eq(insn_ori.spec_pc_wdata)
|
||
|
|
m.d.comb += spec_insn_ori_mem_addr.eq(insn_ori.spec_mem_addr)
|
||
|
|
m.d.comb += spec_insn_ori_mem_rmask.eq(insn_ori.spec_mem_rmask)
|
||
|
|
m.d.comb += spec_insn_ori_mem_wmask.eq(insn_ori.spec_mem_wmask)
|
||
|
|
m.d.comb += spec_insn_ori_mem_wdata.eq(insn_ori.spec_mem_wdata)
|
||
|
|
|
||
|
|
spec_insn_andi_valid = Signal(1)
|
||
|
|
spec_insn_andi_trap = Signal(1)
|
||
|
|
spec_insn_andi_rs1_addr = Signal(5)
|
||
|
|
spec_insn_andi_rs2_addr = Signal(5)
|
||
|
|
spec_insn_andi_rd_addr = Signal(5)
|
||
|
|
spec_insn_andi_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_andi_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_andi_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_andi_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
|
||
|
|
spec_insn_andi_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
|
||
|
|
spec_insn_andi_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
m.submodules.insn_andi = insn_andi = rvfi_insn_andi()
|
||
|
|
m.d.comb += insn_andi.rvfi_valid.eq(self.rvfi_valid)
|
||
|
|
m.d.comb += insn_andi.rvfi_insn.eq(self.rvfi_insn)
|
||
|
|
m.d.comb += insn_andi.rvfi_pc_rdata.eq(self.rvfi_pc_rdata)
|
||
|
|
m.d.comb += insn_andi.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata)
|
||
|
|
m.d.comb += insn_andi.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata)
|
||
|
|
m.d.comb += insn_andi.rvfi_mem_rdata.eq(self.rvfi_mem_rdata)
|
||
|
|
m.d.comb += spec_insn_andi_valid.eq(insn_andi.spec_valid)
|
||
|
|
m.d.comb += spec_insn_andi_trap.eq(insn_andi.spec_trap)
|
||
|
|
m.d.comb += spec_insn_andi_rs1_addr.eq(insn_andi.spec_rs1_addr)
|
||
|
|
m.d.comb += spec_insn_andi_rs2_addr.eq(insn_andi.spec_rs2_addr)
|
||
|
|
m.d.comb += spec_insn_andi_rd_addr.eq(insn_andi.spec_rd_addr)
|
||
|
|
m.d.comb += spec_insn_andi_rd_wdata.eq(insn_andi.spec_rd_wdata)
|
||
|
|
m.d.comb += spec_insn_andi_pc_wdata.eq(insn_andi.spec_pc_wdata)
|
||
|
|
m.d.comb += spec_insn_andi_mem_addr.eq(insn_andi.spec_mem_addr)
|
||
|
|
m.d.comb += spec_insn_andi_mem_rmask.eq(insn_andi.spec_mem_rmask)
|
||
|
|
m.d.comb += spec_insn_andi_mem_wmask.eq(insn_andi.spec_mem_wmask)
|
||
|
|
m.d.comb += spec_insn_andi_mem_wdata.eq(insn_andi.spec_mem_wdata)
|
||
|
|
|
||
|
|
spec_insn_slli_valid = Signal(1)
|
||
|
|
spec_insn_slli_trap = Signal(1)
|
||
|
|
spec_insn_slli_rs1_addr = Signal(5)
|
||
|
|
spec_insn_slli_rs2_addr = Signal(5)
|
||
|
|
spec_insn_slli_rd_addr = Signal(5)
|
||
|
|
spec_insn_slli_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_slli_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_slli_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_slli_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
|
||
|
|
spec_insn_slli_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
|
||
|
|
spec_insn_slli_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
m.submodules.insn_slli = insn_slli = rvfi_insn_slli()
|
||
|
|
m.d.comb += insn_slli.rvfi_valid.eq(self.rvfi_valid)
|
||
|
|
m.d.comb += insn_slli.rvfi_insn.eq(self.rvfi_insn)
|
||
|
|
m.d.comb += insn_slli.rvfi_pc_rdata.eq(self.rvfi_pc_rdata)
|
||
|
|
m.d.comb += insn_slli.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata)
|
||
|
|
m.d.comb += insn_slli.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata)
|
||
|
|
m.d.comb += insn_slli.rvfi_mem_rdata.eq(self.rvfi_mem_rdata)
|
||
|
|
m.d.comb += spec_insn_slli_valid.eq(insn_slli.spec_valid)
|
||
|
|
m.d.comb += spec_insn_slli_trap.eq(insn_slli.spec_trap)
|
||
|
|
m.d.comb += spec_insn_slli_rs1_addr.eq(insn_slli.spec_rs1_addr)
|
||
|
|
m.d.comb += spec_insn_slli_rs2_addr.eq(insn_slli.spec_rs2_addr)
|
||
|
|
m.d.comb += spec_insn_slli_rd_addr.eq(insn_slli.spec_rd_addr)
|
||
|
|
m.d.comb += spec_insn_slli_rd_wdata.eq(insn_slli.spec_rd_wdata)
|
||
|
|
m.d.comb += spec_insn_slli_pc_wdata.eq(insn_slli.spec_pc_wdata)
|
||
|
|
m.d.comb += spec_insn_slli_mem_addr.eq(insn_slli.spec_mem_addr)
|
||
|
|
m.d.comb += spec_insn_slli_mem_rmask.eq(insn_slli.spec_mem_rmask)
|
||
|
|
m.d.comb += spec_insn_slli_mem_wmask.eq(insn_slli.spec_mem_wmask)
|
||
|
|
m.d.comb += spec_insn_slli_mem_wdata.eq(insn_slli.spec_mem_wdata)
|
||
|
|
|
||
|
|
spec_insn_srli_valid = Signal(1)
|
||
|
|
spec_insn_srli_trap = Signal(1)
|
||
|
|
spec_insn_srli_rs1_addr = Signal(5)
|
||
|
|
spec_insn_srli_rs2_addr = Signal(5)
|
||
|
|
spec_insn_srli_rd_addr = Signal(5)
|
||
|
|
spec_insn_srli_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_srli_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_srli_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_srli_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
|
||
|
|
spec_insn_srli_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
|
||
|
|
spec_insn_srli_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
m.submodules.insn_srli = insn_srli = rvfi_insn_srli()
|
||
|
|
m.d.comb += insn_srli.rvfi_valid.eq(self.rvfi_valid)
|
||
|
|
m.d.comb += insn_srli.rvfi_insn.eq(self.rvfi_insn)
|
||
|
|
m.d.comb += insn_srli.rvfi_pc_rdata.eq(self.rvfi_pc_rdata)
|
||
|
|
m.d.comb += insn_srli.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata)
|
||
|
|
m.d.comb += insn_srli.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata)
|
||
|
|
m.d.comb += insn_srli.rvfi_mem_rdata.eq(self.rvfi_mem_rdata)
|
||
|
|
m.d.comb += spec_insn_srli_valid.eq(insn_srli.spec_valid)
|
||
|
|
m.d.comb += spec_insn_srli_trap.eq(insn_srli.spec_trap)
|
||
|
|
m.d.comb += spec_insn_srli_rs1_addr.eq(insn_srli.spec_rs1_addr)
|
||
|
|
m.d.comb += spec_insn_srli_rs2_addr.eq(insn_srli.spec_rs2_addr)
|
||
|
|
m.d.comb += spec_insn_srli_rd_addr.eq(insn_srli.spec_rd_addr)
|
||
|
|
m.d.comb += spec_insn_srli_rd_wdata.eq(insn_srli.spec_rd_wdata)
|
||
|
|
m.d.comb += spec_insn_srli_pc_wdata.eq(insn_srli.spec_pc_wdata)
|
||
|
|
m.d.comb += spec_insn_srli_mem_addr.eq(insn_srli.spec_mem_addr)
|
||
|
|
m.d.comb += spec_insn_srli_mem_rmask.eq(insn_srli.spec_mem_rmask)
|
||
|
|
m.d.comb += spec_insn_srli_mem_wmask.eq(insn_srli.spec_mem_wmask)
|
||
|
|
m.d.comb += spec_insn_srli_mem_wdata.eq(insn_srli.spec_mem_wdata)
|
||
|
|
|
||
|
|
spec_insn_srai_valid = Signal(1)
|
||
|
|
spec_insn_srai_trap = Signal(1)
|
||
|
|
spec_insn_srai_rs1_addr = Signal(5)
|
||
|
|
spec_insn_srai_rs2_addr = Signal(5)
|
||
|
|
spec_insn_srai_rd_addr = Signal(5)
|
||
|
|
spec_insn_srai_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_srai_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_srai_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_srai_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
|
||
|
|
spec_insn_srai_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
|
||
|
|
spec_insn_srai_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
m.submodules.insn_srai = insn_srai = rvfi_insn_srai()
|
||
|
|
m.d.comb += insn_srai.rvfi_valid.eq(self.rvfi_valid)
|
||
|
|
m.d.comb += insn_srai.rvfi_insn.eq(self.rvfi_insn)
|
||
|
|
m.d.comb += insn_srai.rvfi_pc_rdata.eq(self.rvfi_pc_rdata)
|
||
|
|
m.d.comb += insn_srai.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata)
|
||
|
|
m.d.comb += insn_srai.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata)
|
||
|
|
m.d.comb += insn_srai.rvfi_mem_rdata.eq(self.rvfi_mem_rdata)
|
||
|
|
m.d.comb += spec_insn_srai_valid.eq(insn_srai.spec_valid)
|
||
|
|
m.d.comb += spec_insn_srai_trap.eq(insn_srai.spec_trap)
|
||
|
|
m.d.comb += spec_insn_srai_rs1_addr.eq(insn_srai.spec_rs1_addr)
|
||
|
|
m.d.comb += spec_insn_srai_rs2_addr.eq(insn_srai.spec_rs2_addr)
|
||
|
|
m.d.comb += spec_insn_srai_rd_addr.eq(insn_srai.spec_rd_addr)
|
||
|
|
m.d.comb += spec_insn_srai_rd_wdata.eq(insn_srai.spec_rd_wdata)
|
||
|
|
m.d.comb += spec_insn_srai_pc_wdata.eq(insn_srai.spec_pc_wdata)
|
||
|
|
m.d.comb += spec_insn_srai_mem_addr.eq(insn_srai.spec_mem_addr)
|
||
|
|
m.d.comb += spec_insn_srai_mem_rmask.eq(insn_srai.spec_mem_rmask)
|
||
|
|
m.d.comb += spec_insn_srai_mem_wmask.eq(insn_srai.spec_mem_wmask)
|
||
|
|
m.d.comb += spec_insn_srai_mem_wdata.eq(insn_srai.spec_mem_wdata)
|
||
|
|
|
||
|
|
spec_insn_add_valid = Signal(1)
|
||
|
|
spec_insn_add_trap = Signal(1)
|
||
|
|
spec_insn_add_rs1_addr = Signal(5)
|
||
|
|
spec_insn_add_rs2_addr = Signal(5)
|
||
|
|
spec_insn_add_rd_addr = Signal(5)
|
||
|
|
spec_insn_add_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_add_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_add_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_add_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
|
||
|
|
spec_insn_add_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
|
||
|
|
spec_insn_add_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
m.submodules.insn_add = insn_add = rvfi_insn_add()
|
||
|
|
m.d.comb += insn_add.rvfi_valid.eq(self.rvfi_valid)
|
||
|
|
m.d.comb += insn_add.rvfi_insn.eq(self.rvfi_insn)
|
||
|
|
m.d.comb += insn_add.rvfi_pc_rdata.eq(self.rvfi_pc_rdata)
|
||
|
|
m.d.comb += insn_add.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata)
|
||
|
|
m.d.comb += insn_add.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata)
|
||
|
|
m.d.comb += insn_add.rvfi_mem_rdata.eq(self.rvfi_mem_rdata)
|
||
|
|
m.d.comb += spec_insn_add_valid.eq(insn_add.spec_valid)
|
||
|
|
m.d.comb += spec_insn_add_trap.eq(insn_add.spec_trap)
|
||
|
|
m.d.comb += spec_insn_add_rs1_addr.eq(insn_add.spec_rs1_addr)
|
||
|
|
m.d.comb += spec_insn_add_rs2_addr.eq(insn_add.spec_rs2_addr)
|
||
|
|
m.d.comb += spec_insn_add_rd_addr.eq(insn_add.spec_rd_addr)
|
||
|
|
m.d.comb += spec_insn_add_rd_wdata.eq(insn_add.spec_rd_wdata)
|
||
|
|
m.d.comb += spec_insn_add_pc_wdata.eq(insn_add.spec_pc_wdata)
|
||
|
|
m.d.comb += spec_insn_add_mem_addr.eq(insn_add.spec_mem_addr)
|
||
|
|
m.d.comb += spec_insn_add_mem_rmask.eq(insn_add.spec_mem_rmask)
|
||
|
|
m.d.comb += spec_insn_add_mem_wmask.eq(insn_add.spec_mem_wmask)
|
||
|
|
m.d.comb += spec_insn_add_mem_wdata.eq(insn_add.spec_mem_wdata)
|
||
|
|
|
||
|
|
spec_insn_sub_valid = Signal(1)
|
||
|
|
spec_insn_sub_trap = Signal(1)
|
||
|
|
spec_insn_sub_rs1_addr = Signal(5)
|
||
|
|
spec_insn_sub_rs2_addr = Signal(5)
|
||
|
|
spec_insn_sub_rd_addr = Signal(5)
|
||
|
|
spec_insn_sub_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_sub_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_sub_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_sub_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
|
||
|
|
spec_insn_sub_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
|
||
|
|
spec_insn_sub_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
m.submodules.insn_sub = insn_sub = rvfi_insn_sub()
|
||
|
|
m.d.comb += insn_sub.rvfi_valid.eq(self.rvfi_valid)
|
||
|
|
m.d.comb += insn_sub.rvfi_insn.eq(self.rvfi_insn)
|
||
|
|
m.d.comb += insn_sub.rvfi_pc_rdata.eq(self.rvfi_pc_rdata)
|
||
|
|
m.d.comb += insn_sub.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata)
|
||
|
|
m.d.comb += insn_sub.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata)
|
||
|
|
m.d.comb += insn_sub.rvfi_mem_rdata.eq(self.rvfi_mem_rdata)
|
||
|
|
m.d.comb += spec_insn_sub_valid.eq(insn_sub.spec_valid)
|
||
|
|
m.d.comb += spec_insn_sub_trap.eq(insn_sub.spec_trap)
|
||
|
|
m.d.comb += spec_insn_sub_rs1_addr.eq(insn_sub.spec_rs1_addr)
|
||
|
|
m.d.comb += spec_insn_sub_rs2_addr.eq(insn_sub.spec_rs2_addr)
|
||
|
|
m.d.comb += spec_insn_sub_rd_addr.eq(insn_sub.spec_rd_addr)
|
||
|
|
m.d.comb += spec_insn_sub_rd_wdata.eq(insn_sub.spec_rd_wdata)
|
||
|
|
m.d.comb += spec_insn_sub_pc_wdata.eq(insn_sub.spec_pc_wdata)
|
||
|
|
m.d.comb += spec_insn_sub_mem_addr.eq(insn_sub.spec_mem_addr)
|
||
|
|
m.d.comb += spec_insn_sub_mem_rmask.eq(insn_sub.spec_mem_rmask)
|
||
|
|
m.d.comb += spec_insn_sub_mem_wmask.eq(insn_sub.spec_mem_wmask)
|
||
|
|
m.d.comb += spec_insn_sub_mem_wdata.eq(insn_sub.spec_mem_wdata)
|
||
|
|
|
||
|
|
spec_insn_sll_valid = Signal(1)
|
||
|
|
spec_insn_sll_trap = Signal(1)
|
||
|
|
spec_insn_sll_rs1_addr = Signal(5)
|
||
|
|
spec_insn_sll_rs2_addr = Signal(5)
|
||
|
|
spec_insn_sll_rd_addr = Signal(5)
|
||
|
|
spec_insn_sll_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_sll_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_sll_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_sll_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
|
||
|
|
spec_insn_sll_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
|
||
|
|
spec_insn_sll_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
m.submodules.insn_sll = insn_sll = rvfi_insn_sll()
|
||
|
|
m.d.comb += insn_sll.rvfi_valid.eq(self.rvfi_valid)
|
||
|
|
m.d.comb += insn_sll.rvfi_insn.eq(self.rvfi_insn)
|
||
|
|
m.d.comb += insn_sll.rvfi_pc_rdata.eq(self.rvfi_pc_rdata)
|
||
|
|
m.d.comb += insn_sll.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata)
|
||
|
|
m.d.comb += insn_sll.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata)
|
||
|
|
m.d.comb += insn_sll.rvfi_mem_rdata.eq(self.rvfi_mem_rdata)
|
||
|
|
m.d.comb += spec_insn_sll_valid.eq(insn_sll.spec_valid)
|
||
|
|
m.d.comb += spec_insn_sll_trap.eq(insn_sll.spec_trap)
|
||
|
|
m.d.comb += spec_insn_sll_rs1_addr.eq(insn_sll.spec_rs1_addr)
|
||
|
|
m.d.comb += spec_insn_sll_rs2_addr.eq(insn_sll.spec_rs2_addr)
|
||
|
|
m.d.comb += spec_insn_sll_rd_addr.eq(insn_sll.spec_rd_addr)
|
||
|
|
m.d.comb += spec_insn_sll_rd_wdata.eq(insn_sll.spec_rd_wdata)
|
||
|
|
m.d.comb += spec_insn_sll_pc_wdata.eq(insn_sll.spec_pc_wdata)
|
||
|
|
m.d.comb += spec_insn_sll_mem_addr.eq(insn_sll.spec_mem_addr)
|
||
|
|
m.d.comb += spec_insn_sll_mem_rmask.eq(insn_sll.spec_mem_rmask)
|
||
|
|
m.d.comb += spec_insn_sll_mem_wmask.eq(insn_sll.spec_mem_wmask)
|
||
|
|
m.d.comb += spec_insn_sll_mem_wdata.eq(insn_sll.spec_mem_wdata)
|
||
|
|
|
||
|
|
spec_insn_slt_valid = Signal(1)
|
||
|
|
spec_insn_slt_trap = Signal(1)
|
||
|
|
spec_insn_slt_rs1_addr = Signal(5)
|
||
|
|
spec_insn_slt_rs2_addr = Signal(5)
|
||
|
|
spec_insn_slt_rd_addr = Signal(5)
|
||
|
|
spec_insn_slt_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_slt_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_slt_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_slt_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
|
||
|
|
spec_insn_slt_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
|
||
|
|
spec_insn_slt_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
m.submodules.insn_slt = insn_slt = rvfi_insn_slt()
|
||
|
|
m.d.comb += insn_slt.rvfi_valid.eq(self.rvfi_valid)
|
||
|
|
m.d.comb += insn_slt.rvfi_insn.eq(self.rvfi_insn)
|
||
|
|
m.d.comb += insn_slt.rvfi_pc_rdata.eq(self.rvfi_pc_rdata)
|
||
|
|
m.d.comb += insn_slt.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata)
|
||
|
|
m.d.comb += insn_slt.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata)
|
||
|
|
m.d.comb += insn_slt.rvfi_mem_rdata.eq(self.rvfi_mem_rdata)
|
||
|
|
m.d.comb += spec_insn_slt_valid.eq(insn_slt.spec_valid)
|
||
|
|
m.d.comb += spec_insn_slt_trap.eq(insn_slt.spec_trap)
|
||
|
|
m.d.comb += spec_insn_slt_rs1_addr.eq(insn_slt.spec_rs1_addr)
|
||
|
|
m.d.comb += spec_insn_slt_rs2_addr.eq(insn_slt.spec_rs2_addr)
|
||
|
|
m.d.comb += spec_insn_slt_rd_addr.eq(insn_slt.spec_rd_addr)
|
||
|
|
m.d.comb += spec_insn_slt_rd_wdata.eq(insn_slt.spec_rd_wdata)
|
||
|
|
m.d.comb += spec_insn_slt_pc_wdata.eq(insn_slt.spec_pc_wdata)
|
||
|
|
m.d.comb += spec_insn_slt_mem_addr.eq(insn_slt.spec_mem_addr)
|
||
|
|
m.d.comb += spec_insn_slt_mem_rmask.eq(insn_slt.spec_mem_rmask)
|
||
|
|
m.d.comb += spec_insn_slt_mem_wmask.eq(insn_slt.spec_mem_wmask)
|
||
|
|
m.d.comb += spec_insn_slt_mem_wdata.eq(insn_slt.spec_mem_wdata)
|
||
|
|
|
||
|
|
spec_insn_sltu_valid = Signal(1)
|
||
|
|
spec_insn_sltu_trap = Signal(1)
|
||
|
|
spec_insn_sltu_rs1_addr = Signal(5)
|
||
|
|
spec_insn_sltu_rs2_addr = Signal(5)
|
||
|
|
spec_insn_sltu_rd_addr = Signal(5)
|
||
|
|
spec_insn_sltu_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_sltu_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_sltu_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_sltu_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
|
||
|
|
spec_insn_sltu_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
|
||
|
|
spec_insn_sltu_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
m.submodules.insn_sltu = insn_sltu = rvfi_insn_sltu()
|
||
|
|
m.d.comb += insn_sltu.rvfi_valid.eq(self.rvfi_valid)
|
||
|
|
m.d.comb += insn_sltu.rvfi_insn.eq(self.rvfi_insn)
|
||
|
|
m.d.comb += insn_sltu.rvfi_pc_rdata.eq(self.rvfi_pc_rdata)
|
||
|
|
m.d.comb += insn_sltu.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata)
|
||
|
|
m.d.comb += insn_sltu.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata)
|
||
|
|
m.d.comb += insn_sltu.rvfi_mem_rdata.eq(self.rvfi_mem_rdata)
|
||
|
|
m.d.comb += spec_insn_sltu_valid.eq(insn_sltu.spec_valid)
|
||
|
|
m.d.comb += spec_insn_sltu_trap.eq(insn_sltu.spec_trap)
|
||
|
|
m.d.comb += spec_insn_sltu_rs1_addr.eq(insn_sltu.spec_rs1_addr)
|
||
|
|
m.d.comb += spec_insn_sltu_rs2_addr.eq(insn_sltu.spec_rs2_addr)
|
||
|
|
m.d.comb += spec_insn_sltu_rd_addr.eq(insn_sltu.spec_rd_addr)
|
||
|
|
m.d.comb += spec_insn_sltu_rd_wdata.eq(insn_sltu.spec_rd_wdata)
|
||
|
|
m.d.comb += spec_insn_sltu_pc_wdata.eq(insn_sltu.spec_pc_wdata)
|
||
|
|
m.d.comb += spec_insn_sltu_mem_addr.eq(insn_sltu.spec_mem_addr)
|
||
|
|
m.d.comb += spec_insn_sltu_mem_rmask.eq(insn_sltu.spec_mem_rmask)
|
||
|
|
m.d.comb += spec_insn_sltu_mem_wmask.eq(insn_sltu.spec_mem_wmask)
|
||
|
|
m.d.comb += spec_insn_sltu_mem_wdata.eq(insn_sltu.spec_mem_wdata)
|
||
|
|
|
||
|
|
spec_insn_xor_valid = Signal(1)
|
||
|
|
spec_insn_xor_trap = Signal(1)
|
||
|
|
spec_insn_xor_rs1_addr = Signal(5)
|
||
|
|
spec_insn_xor_rs2_addr = Signal(5)
|
||
|
|
spec_insn_xor_rd_addr = Signal(5)
|
||
|
|
spec_insn_xor_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_xor_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_xor_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_xor_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
|
||
|
|
spec_insn_xor_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
|
||
|
|
spec_insn_xor_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
m.submodules.insn_xor = insn_xor = rvfi_insn_xor()
|
||
|
|
m.d.comb += insn_xor.rvfi_valid.eq(self.rvfi_valid)
|
||
|
|
m.d.comb += insn_xor.rvfi_insn.eq(self.rvfi_insn)
|
||
|
|
m.d.comb += insn_xor.rvfi_pc_rdata.eq(self.rvfi_pc_rdata)
|
||
|
|
m.d.comb += insn_xor.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata)
|
||
|
|
m.d.comb += insn_xor.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata)
|
||
|
|
m.d.comb += insn_xor.rvfi_mem_rdata.eq(self.rvfi_mem_rdata)
|
||
|
|
m.d.comb += spec_insn_xor_valid.eq(insn_xor.spec_valid)
|
||
|
|
m.d.comb += spec_insn_xor_trap.eq(insn_xor.spec_trap)
|
||
|
|
m.d.comb += spec_insn_xor_rs1_addr.eq(insn_xor.spec_rs1_addr)
|
||
|
|
m.d.comb += spec_insn_xor_rs2_addr.eq(insn_xor.spec_rs2_addr)
|
||
|
|
m.d.comb += spec_insn_xor_rd_addr.eq(insn_xor.spec_rd_addr)
|
||
|
|
m.d.comb += spec_insn_xor_rd_wdata.eq(insn_xor.spec_rd_wdata)
|
||
|
|
m.d.comb += spec_insn_xor_pc_wdata.eq(insn_xor.spec_pc_wdata)
|
||
|
|
m.d.comb += spec_insn_xor_mem_addr.eq(insn_xor.spec_mem_addr)
|
||
|
|
m.d.comb += spec_insn_xor_mem_rmask.eq(insn_xor.spec_mem_rmask)
|
||
|
|
m.d.comb += spec_insn_xor_mem_wmask.eq(insn_xor.spec_mem_wmask)
|
||
|
|
m.d.comb += spec_insn_xor_mem_wdata.eq(insn_xor.spec_mem_wdata)
|
||
|
|
|
||
|
|
spec_insn_srl_valid = Signal(1)
|
||
|
|
spec_insn_srl_trap = Signal(1)
|
||
|
|
spec_insn_srl_rs1_addr = Signal(5)
|
||
|
|
spec_insn_srl_rs2_addr = Signal(5)
|
||
|
|
spec_insn_srl_rd_addr = Signal(5)
|
||
|
|
spec_insn_srl_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_srl_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_srl_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_srl_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
|
||
|
|
spec_insn_srl_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
|
||
|
|
spec_insn_srl_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
m.submodules.insn_srl = insn_srl = rvfi_insn_srl()
|
||
|
|
m.d.comb += insn_srl.rvfi_valid.eq(self.rvfi_valid)
|
||
|
|
m.d.comb += insn_srl.rvfi_insn.eq(self.rvfi_insn)
|
||
|
|
m.d.comb += insn_srl.rvfi_pc_rdata.eq(self.rvfi_pc_rdata)
|
||
|
|
m.d.comb += insn_srl.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata)
|
||
|
|
m.d.comb += insn_srl.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata)
|
||
|
|
m.d.comb += insn_srl.rvfi_mem_rdata.eq(self.rvfi_mem_rdata)
|
||
|
|
m.d.comb += spec_insn_srl_valid.eq(insn_srl.spec_valid)
|
||
|
|
m.d.comb += spec_insn_srl_trap.eq(insn_srl.spec_trap)
|
||
|
|
m.d.comb += spec_insn_srl_rs1_addr.eq(insn_srl.spec_rs1_addr)
|
||
|
|
m.d.comb += spec_insn_srl_rs2_addr.eq(insn_srl.spec_rs2_addr)
|
||
|
|
m.d.comb += spec_insn_srl_rd_addr.eq(insn_srl.spec_rd_addr)
|
||
|
|
m.d.comb += spec_insn_srl_rd_wdata.eq(insn_srl.spec_rd_wdata)
|
||
|
|
m.d.comb += spec_insn_srl_pc_wdata.eq(insn_srl.spec_pc_wdata)
|
||
|
|
m.d.comb += spec_insn_srl_mem_addr.eq(insn_srl.spec_mem_addr)
|
||
|
|
m.d.comb += spec_insn_srl_mem_rmask.eq(insn_srl.spec_mem_rmask)
|
||
|
|
m.d.comb += spec_insn_srl_mem_wmask.eq(insn_srl.spec_mem_wmask)
|
||
|
|
m.d.comb += spec_insn_srl_mem_wdata.eq(insn_srl.spec_mem_wdata)
|
||
|
|
|
||
|
|
spec_insn_sra_valid = Signal(1)
|
||
|
|
spec_insn_sra_trap = Signal(1)
|
||
|
|
spec_insn_sra_rs1_addr = Signal(5)
|
||
|
|
spec_insn_sra_rs2_addr = Signal(5)
|
||
|
|
spec_insn_sra_rd_addr = Signal(5)
|
||
|
|
spec_insn_sra_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_sra_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_sra_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_sra_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
|
||
|
|
spec_insn_sra_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
|
||
|
|
spec_insn_sra_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
m.submodules.insn_sra = insn_sra = rvfi_insn_sra()
|
||
|
|
m.d.comb += insn_sra.rvfi_valid.eq(self.rvfi_valid)
|
||
|
|
m.d.comb += insn_sra.rvfi_insn.eq(self.rvfi_insn)
|
||
|
|
m.d.comb += insn_sra.rvfi_pc_rdata.eq(self.rvfi_pc_rdata)
|
||
|
|
m.d.comb += insn_sra.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata)
|
||
|
|
m.d.comb += insn_sra.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata)
|
||
|
|
m.d.comb += insn_sra.rvfi_mem_rdata.eq(self.rvfi_mem_rdata)
|
||
|
|
m.d.comb += spec_insn_sra_valid.eq(insn_sra.spec_valid)
|
||
|
|
m.d.comb += spec_insn_sra_trap.eq(insn_sra.spec_trap)
|
||
|
|
m.d.comb += spec_insn_sra_rs1_addr.eq(insn_sra.spec_rs1_addr)
|
||
|
|
m.d.comb += spec_insn_sra_rs2_addr.eq(insn_sra.spec_rs2_addr)
|
||
|
|
m.d.comb += spec_insn_sra_rd_addr.eq(insn_sra.spec_rd_addr)
|
||
|
|
m.d.comb += spec_insn_sra_rd_wdata.eq(insn_sra.spec_rd_wdata)
|
||
|
|
m.d.comb += spec_insn_sra_pc_wdata.eq(insn_sra.spec_pc_wdata)
|
||
|
|
m.d.comb += spec_insn_sra_mem_addr.eq(insn_sra.spec_mem_addr)
|
||
|
|
m.d.comb += spec_insn_sra_mem_rmask.eq(insn_sra.spec_mem_rmask)
|
||
|
|
m.d.comb += spec_insn_sra_mem_wmask.eq(insn_sra.spec_mem_wmask)
|
||
|
|
m.d.comb += spec_insn_sra_mem_wdata.eq(insn_sra.spec_mem_wdata)
|
||
|
|
|
||
|
|
spec_insn_or_valid = Signal(1)
|
||
|
|
spec_insn_or_trap = Signal(1)
|
||
|
|
spec_insn_or_rs1_addr = Signal(5)
|
||
|
|
spec_insn_or_rs2_addr = Signal(5)
|
||
|
|
spec_insn_or_rd_addr = Signal(5)
|
||
|
|
spec_insn_or_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_or_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_or_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_or_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
|
||
|
|
spec_insn_or_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
|
||
|
|
spec_insn_or_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
m.submodules.insn_or = insn_or = rvfi_insn_or()
|
||
|
|
m.d.comb += insn_or.rvfi_valid.eq(self.rvfi_valid)
|
||
|
|
m.d.comb += insn_or.rvfi_insn.eq(self.rvfi_insn)
|
||
|
|
m.d.comb += insn_or.rvfi_pc_rdata.eq(self.rvfi_pc_rdata)
|
||
|
|
m.d.comb += insn_or.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata)
|
||
|
|
m.d.comb += insn_or.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata)
|
||
|
|
m.d.comb += insn_or.rvfi_mem_rdata.eq(self.rvfi_mem_rdata)
|
||
|
|
m.d.comb += spec_insn_or_valid.eq(insn_or.spec_valid)
|
||
|
|
m.d.comb += spec_insn_or_trap.eq(insn_or.spec_trap)
|
||
|
|
m.d.comb += spec_insn_or_rs1_addr.eq(insn_or.spec_rs1_addr)
|
||
|
|
m.d.comb += spec_insn_or_rs2_addr.eq(insn_or.spec_rs2_addr)
|
||
|
|
m.d.comb += spec_insn_or_rd_addr.eq(insn_or.spec_rd_addr)
|
||
|
|
m.d.comb += spec_insn_or_rd_wdata.eq(insn_or.spec_rd_wdata)
|
||
|
|
m.d.comb += spec_insn_or_pc_wdata.eq(insn_or.spec_pc_wdata)
|
||
|
|
m.d.comb += spec_insn_or_mem_addr.eq(insn_or.spec_mem_addr)
|
||
|
|
m.d.comb += spec_insn_or_mem_rmask.eq(insn_or.spec_mem_rmask)
|
||
|
|
m.d.comb += spec_insn_or_mem_wmask.eq(insn_or.spec_mem_wmask)
|
||
|
|
m.d.comb += spec_insn_or_mem_wdata.eq(insn_or.spec_mem_wdata)
|
||
|
|
|
||
|
|
spec_insn_and_valid = Signal(1)
|
||
|
|
spec_insn_and_trap = Signal(1)
|
||
|
|
spec_insn_and_rs1_addr = Signal(5)
|
||
|
|
spec_insn_and_rs2_addr = Signal(5)
|
||
|
|
spec_insn_and_rd_addr = Signal(5)
|
||
|
|
spec_insn_and_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_and_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_and_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_and_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
|
||
|
|
spec_insn_and_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
|
||
|
|
spec_insn_and_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
m.submodules.insn_and = insn_and = rvfi_insn_and()
|
||
|
|
m.d.comb += insn_and.rvfi_valid.eq(self.rvfi_valid)
|
||
|
|
m.d.comb += insn_and.rvfi_insn.eq(self.rvfi_insn)
|
||
|
|
m.d.comb += insn_and.rvfi_pc_rdata.eq(self.rvfi_pc_rdata)
|
||
|
|
m.d.comb += insn_and.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata)
|
||
|
|
m.d.comb += insn_and.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata)
|
||
|
|
m.d.comb += insn_and.rvfi_mem_rdata.eq(self.rvfi_mem_rdata)
|
||
|
|
m.d.comb += spec_insn_and_valid.eq(insn_and.spec_valid)
|
||
|
|
m.d.comb += spec_insn_and_trap.eq(insn_and.spec_trap)
|
||
|
|
m.d.comb += spec_insn_and_rs1_addr.eq(insn_and.spec_rs1_addr)
|
||
|
|
m.d.comb += spec_insn_and_rs2_addr.eq(insn_and.spec_rs2_addr)
|
||
|
|
m.d.comb += spec_insn_and_rd_addr.eq(insn_and.spec_rd_addr)
|
||
|
|
m.d.comb += spec_insn_and_rd_wdata.eq(insn_and.spec_rd_wdata)
|
||
|
|
m.d.comb += spec_insn_and_pc_wdata.eq(insn_and.spec_pc_wdata)
|
||
|
|
m.d.comb += spec_insn_and_mem_addr.eq(insn_and.spec_mem_addr)
|
||
|
|
m.d.comb += spec_insn_and_mem_rmask.eq(insn_and.spec_mem_rmask)
|
||
|
|
m.d.comb += spec_insn_and_mem_wmask.eq(insn_and.spec_mem_wmask)
|
||
|
|
m.d.comb += spec_insn_and_mem_wdata.eq(insn_and.spec_mem_wdata)
|
||
|
|
|
||
|
|
spec_insn_mul_valid = Signal(1)
|
||
|
|
spec_insn_mul_trap = Signal(1)
|
||
|
|
spec_insn_mul_rs1_addr = Signal(5)
|
||
|
|
spec_insn_mul_rs2_addr = Signal(5)
|
||
|
|
spec_insn_mul_rd_addr = Signal(5)
|
||
|
|
spec_insn_mul_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_mul_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_mul_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_mul_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
|
||
|
|
spec_insn_mul_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
|
||
|
|
spec_insn_mul_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
m.submodules.insn_mul = insn_mul = rvfi_insn_mul()
|
||
|
|
m.d.comb += insn_mul.rvfi_valid.eq(self.rvfi_valid)
|
||
|
|
m.d.comb += insn_mul.rvfi_insn.eq(self.rvfi_insn)
|
||
|
|
m.d.comb += insn_mul.rvfi_pc_rdata.eq(self.rvfi_pc_rdata)
|
||
|
|
m.d.comb += insn_mul.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata)
|
||
|
|
m.d.comb += insn_mul.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata)
|
||
|
|
m.d.comb += insn_mul.rvfi_mem_rdata.eq(self.rvfi_mem_rdata)
|
||
|
|
m.d.comb += spec_insn_mul_valid.eq(insn_mul.spec_valid)
|
||
|
|
m.d.comb += spec_insn_mul_trap.eq(insn_mul.spec_trap)
|
||
|
|
m.d.comb += spec_insn_mul_rs1_addr.eq(insn_mul.spec_rs1_addr)
|
||
|
|
m.d.comb += spec_insn_mul_rs2_addr.eq(insn_mul.spec_rs2_addr)
|
||
|
|
m.d.comb += spec_insn_mul_rd_addr.eq(insn_mul.spec_rd_addr)
|
||
|
|
m.d.comb += spec_insn_mul_rd_wdata.eq(insn_mul.spec_rd_wdata)
|
||
|
|
m.d.comb += spec_insn_mul_pc_wdata.eq(insn_mul.spec_pc_wdata)
|
||
|
|
m.d.comb += spec_insn_mul_mem_addr.eq(insn_mul.spec_mem_addr)
|
||
|
|
m.d.comb += spec_insn_mul_mem_rmask.eq(insn_mul.spec_mem_rmask)
|
||
|
|
m.d.comb += spec_insn_mul_mem_wmask.eq(insn_mul.spec_mem_wmask)
|
||
|
|
m.d.comb += spec_insn_mul_mem_wdata.eq(insn_mul.spec_mem_wdata)
|
||
|
|
|
||
|
|
spec_insn_mulh_valid = Signal(1)
|
||
|
|
spec_insn_mulh_trap = Signal(1)
|
||
|
|
spec_insn_mulh_rs1_addr = Signal(5)
|
||
|
|
spec_insn_mulh_rs2_addr = Signal(5)
|
||
|
|
spec_insn_mulh_rd_addr = Signal(5)
|
||
|
|
spec_insn_mulh_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_mulh_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_mulh_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_mulh_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
|
||
|
|
spec_insn_mulh_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
|
||
|
|
spec_insn_mulh_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
m.submodules.insn_mulh = insn_mulh = rvfi_insn_mulh()
|
||
|
|
m.d.comb += insn_mulh.rvfi_valid.eq(self.rvfi_valid)
|
||
|
|
m.d.comb += insn_mulh.rvfi_insn.eq(self.rvfi_insn)
|
||
|
|
m.d.comb += insn_mulh.rvfi_pc_rdata.eq(self.rvfi_pc_rdata)
|
||
|
|
m.d.comb += insn_mulh.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata)
|
||
|
|
m.d.comb += insn_mulh.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata)
|
||
|
|
m.d.comb += insn_mulh.rvfi_mem_rdata.eq(self.rvfi_mem_rdata)
|
||
|
|
m.d.comb += spec_insn_mulh_valid.eq(insn_mulh.spec_valid)
|
||
|
|
m.d.comb += spec_insn_mulh_trap.eq(insn_mulh.spec_trap)
|
||
|
|
m.d.comb += spec_insn_mulh_rs1_addr.eq(insn_mulh.spec_rs1_addr)
|
||
|
|
m.d.comb += spec_insn_mulh_rs2_addr.eq(insn_mulh.spec_rs2_addr)
|
||
|
|
m.d.comb += spec_insn_mulh_rd_addr.eq(insn_mulh.spec_rd_addr)
|
||
|
|
m.d.comb += spec_insn_mulh_rd_wdata.eq(insn_mulh.spec_rd_wdata)
|
||
|
|
m.d.comb += spec_insn_mulh_pc_wdata.eq(insn_mulh.spec_pc_wdata)
|
||
|
|
m.d.comb += spec_insn_mulh_mem_addr.eq(insn_mulh.spec_mem_addr)
|
||
|
|
m.d.comb += spec_insn_mulh_mem_rmask.eq(insn_mulh.spec_mem_rmask)
|
||
|
|
m.d.comb += spec_insn_mulh_mem_wmask.eq(insn_mulh.spec_mem_wmask)
|
||
|
|
m.d.comb += spec_insn_mulh_mem_wdata.eq(insn_mulh.spec_mem_wdata)
|
||
|
|
|
||
|
|
spec_insn_mulhsu_valid = Signal(1)
|
||
|
|
spec_insn_mulhsu_trap = Signal(1)
|
||
|
|
spec_insn_mulhsu_rs1_addr = Signal(5)
|
||
|
|
spec_insn_mulhsu_rs2_addr = Signal(5)
|
||
|
|
spec_insn_mulhsu_rd_addr = Signal(5)
|
||
|
|
spec_insn_mulhsu_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_mulhsu_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_mulhsu_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_mulhsu_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
|
||
|
|
spec_insn_mulhsu_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
|
||
|
|
spec_insn_mulhsu_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
m.submodules.insn_mulhsu = insn_mulhsu = rvfi_insn_mulhsu()
|
||
|
|
m.d.comb += insn_mulhsu.rvfi_valid.eq(self.rvfi_valid)
|
||
|
|
m.d.comb += insn_mulhsu.rvfi_insn.eq(self.rvfi_insn)
|
||
|
|
m.d.comb += insn_mulhsu.rvfi_pc_rdata.eq(self.rvfi_pc_rdata)
|
||
|
|
m.d.comb += insn_mulhsu.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata)
|
||
|
|
m.d.comb += insn_mulhsu.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata)
|
||
|
|
m.d.comb += insn_mulhsu.rvfi_mem_rdata.eq(self.rvfi_mem_rdata)
|
||
|
|
m.d.comb += spec_insn_mulhsu_valid.eq(insn_mulhsu.spec_valid)
|
||
|
|
m.d.comb += spec_insn_mulhsu_trap.eq(insn_mulhsu.spec_trap)
|
||
|
|
m.d.comb += spec_insn_mulhsu_rs1_addr.eq(insn_mulhsu.spec_rs1_addr)
|
||
|
|
m.d.comb += spec_insn_mulhsu_rs2_addr.eq(insn_mulhsu.spec_rs2_addr)
|
||
|
|
m.d.comb += spec_insn_mulhsu_rd_addr.eq(insn_mulhsu.spec_rd_addr)
|
||
|
|
m.d.comb += spec_insn_mulhsu_rd_wdata.eq(insn_mulhsu.spec_rd_wdata)
|
||
|
|
m.d.comb += spec_insn_mulhsu_pc_wdata.eq(insn_mulhsu.spec_pc_wdata)
|
||
|
|
m.d.comb += spec_insn_mulhsu_mem_addr.eq(insn_mulhsu.spec_mem_addr)
|
||
|
|
m.d.comb += spec_insn_mulhsu_mem_rmask.eq(insn_mulhsu.spec_mem_rmask)
|
||
|
|
m.d.comb += spec_insn_mulhsu_mem_wmask.eq(insn_mulhsu.spec_mem_wmask)
|
||
|
|
m.d.comb += spec_insn_mulhsu_mem_wdata.eq(insn_mulhsu.spec_mem_wdata)
|
||
|
|
|
||
|
|
spec_insn_mulhu_valid = Signal(1)
|
||
|
|
spec_insn_mulhu_trap = Signal(1)
|
||
|
|
spec_insn_mulhu_rs1_addr = Signal(5)
|
||
|
|
spec_insn_mulhu_rs2_addr = Signal(5)
|
||
|
|
spec_insn_mulhu_rd_addr = Signal(5)
|
||
|
|
spec_insn_mulhu_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_mulhu_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_mulhu_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_mulhu_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
|
||
|
|
spec_insn_mulhu_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
|
||
|
|
spec_insn_mulhu_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
m.submodules.insn_mulhu = insn_mulhu = rvfi_insn_mulhu()
|
||
|
|
m.d.comb += insn_mulhu.rvfi_valid.eq(self.rvfi_valid)
|
||
|
|
m.d.comb += insn_mulhu.rvfi_insn.eq(self.rvfi_insn)
|
||
|
|
m.d.comb += insn_mulhu.rvfi_pc_rdata.eq(self.rvfi_pc_rdata)
|
||
|
|
m.d.comb += insn_mulhu.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata)
|
||
|
|
m.d.comb += insn_mulhu.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata)
|
||
|
|
m.d.comb += insn_mulhu.rvfi_mem_rdata.eq(self.rvfi_mem_rdata)
|
||
|
|
m.d.comb += spec_insn_mulhu_valid.eq(insn_mulhu.spec_valid)
|
||
|
|
m.d.comb += spec_insn_mulhu_trap.eq(insn_mulhu.spec_trap)
|
||
|
|
m.d.comb += spec_insn_mulhu_rs1_addr.eq(insn_mulhu.spec_rs1_addr)
|
||
|
|
m.d.comb += spec_insn_mulhu_rs2_addr.eq(insn_mulhu.spec_rs2_addr)
|
||
|
|
m.d.comb += spec_insn_mulhu_rd_addr.eq(insn_mulhu.spec_rd_addr)
|
||
|
|
m.d.comb += spec_insn_mulhu_rd_wdata.eq(insn_mulhu.spec_rd_wdata)
|
||
|
|
m.d.comb += spec_insn_mulhu_pc_wdata.eq(insn_mulhu.spec_pc_wdata)
|
||
|
|
m.d.comb += spec_insn_mulhu_mem_addr.eq(insn_mulhu.spec_mem_addr)
|
||
|
|
m.d.comb += spec_insn_mulhu_mem_rmask.eq(insn_mulhu.spec_mem_rmask)
|
||
|
|
m.d.comb += spec_insn_mulhu_mem_wmask.eq(insn_mulhu.spec_mem_wmask)
|
||
|
|
m.d.comb += spec_insn_mulhu_mem_wdata.eq(insn_mulhu.spec_mem_wdata)
|
||
|
|
|
||
|
|
spec_insn_div_valid = Signal(1)
|
||
|
|
spec_insn_div_trap = Signal(1)
|
||
|
|
spec_insn_div_rs1_addr = Signal(5)
|
||
|
|
spec_insn_div_rs2_addr = Signal(5)
|
||
|
|
spec_insn_div_rd_addr = Signal(5)
|
||
|
|
spec_insn_div_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_div_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_div_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_div_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
|
||
|
|
spec_insn_div_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
|
||
|
|
spec_insn_div_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
m.submodules.insn_div = insn_div = rvfi_insn_div()
|
||
|
|
m.d.comb += insn_div.rvfi_valid.eq(self.rvfi_valid)
|
||
|
|
m.d.comb += insn_div.rvfi_insn.eq(self.rvfi_insn)
|
||
|
|
m.d.comb += insn_div.rvfi_pc_rdata.eq(self.rvfi_pc_rdata)
|
||
|
|
m.d.comb += insn_div.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata)
|
||
|
|
m.d.comb += insn_div.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata)
|
||
|
|
m.d.comb += insn_div.rvfi_mem_rdata.eq(self.rvfi_mem_rdata)
|
||
|
|
m.d.comb += spec_insn_div_valid.eq(insn_div.spec_valid)
|
||
|
|
m.d.comb += spec_insn_div_trap.eq(insn_div.spec_trap)
|
||
|
|
m.d.comb += spec_insn_div_rs1_addr.eq(insn_div.spec_rs1_addr)
|
||
|
|
m.d.comb += spec_insn_div_rs2_addr.eq(insn_div.spec_rs2_addr)
|
||
|
|
m.d.comb += spec_insn_div_rd_addr.eq(insn_div.spec_rd_addr)
|
||
|
|
m.d.comb += spec_insn_div_rd_wdata.eq(insn_div.spec_rd_wdata)
|
||
|
|
m.d.comb += spec_insn_div_pc_wdata.eq(insn_div.spec_pc_wdata)
|
||
|
|
m.d.comb += spec_insn_div_mem_addr.eq(insn_div.spec_mem_addr)
|
||
|
|
m.d.comb += spec_insn_div_mem_rmask.eq(insn_div.spec_mem_rmask)
|
||
|
|
m.d.comb += spec_insn_div_mem_wmask.eq(insn_div.spec_mem_wmask)
|
||
|
|
m.d.comb += spec_insn_div_mem_wdata.eq(insn_div.spec_mem_wdata)
|
||
|
|
|
||
|
|
spec_insn_divu_valid = Signal(1)
|
||
|
|
spec_insn_divu_trap = Signal(1)
|
||
|
|
spec_insn_divu_rs1_addr = Signal(5)
|
||
|
|
spec_insn_divu_rs2_addr = Signal(5)
|
||
|
|
spec_insn_divu_rd_addr = Signal(5)
|
||
|
|
spec_insn_divu_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_divu_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_divu_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_divu_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
|
||
|
|
spec_insn_divu_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
|
||
|
|
spec_insn_divu_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
m.submodules.insn_divu = insn_divu = rvfi_insn_divu()
|
||
|
|
m.d.comb += insn_divu.rvfi_valid.eq(self.rvfi_valid)
|
||
|
|
m.d.comb += insn_divu.rvfi_insn.eq(self.rvfi_insn)
|
||
|
|
m.d.comb += insn_divu.rvfi_pc_rdata.eq(self.rvfi_pc_rdata)
|
||
|
|
m.d.comb += insn_divu.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata)
|
||
|
|
m.d.comb += insn_divu.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata)
|
||
|
|
m.d.comb += insn_divu.rvfi_mem_rdata.eq(self.rvfi_mem_rdata)
|
||
|
|
m.d.comb += spec_insn_divu_valid.eq(insn_divu.spec_valid)
|
||
|
|
m.d.comb += spec_insn_divu_trap.eq(insn_divu.spec_trap)
|
||
|
|
m.d.comb += spec_insn_divu_rs1_addr.eq(insn_divu.spec_rs1_addr)
|
||
|
|
m.d.comb += spec_insn_divu_rs2_addr.eq(insn_divu.spec_rs2_addr)
|
||
|
|
m.d.comb += spec_insn_divu_rd_addr.eq(insn_divu.spec_rd_addr)
|
||
|
|
m.d.comb += spec_insn_divu_rd_wdata.eq(insn_divu.spec_rd_wdata)
|
||
|
|
m.d.comb += spec_insn_divu_pc_wdata.eq(insn_divu.spec_pc_wdata)
|
||
|
|
m.d.comb += spec_insn_divu_mem_addr.eq(insn_divu.spec_mem_addr)
|
||
|
|
m.d.comb += spec_insn_divu_mem_rmask.eq(insn_divu.spec_mem_rmask)
|
||
|
|
m.d.comb += spec_insn_divu_mem_wmask.eq(insn_divu.spec_mem_wmask)
|
||
|
|
m.d.comb += spec_insn_divu_mem_wdata.eq(insn_divu.spec_mem_wdata)
|
||
|
|
|
||
|
|
spec_insn_rem_valid = Signal(1)
|
||
|
|
spec_insn_rem_trap = Signal(1)
|
||
|
|
spec_insn_rem_rs1_addr = Signal(5)
|
||
|
|
spec_insn_rem_rs2_addr = Signal(5)
|
||
|
|
spec_insn_rem_rd_addr = Signal(5)
|
||
|
|
spec_insn_rem_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_rem_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_rem_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_rem_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
|
||
|
|
spec_insn_rem_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
|
||
|
|
spec_insn_rem_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
m.submodules.insn_rem = insn_rem = rvfi_insn_rem()
|
||
|
|
m.d.comb += insn_rem.rvfi_valid.eq(self.rvfi_valid)
|
||
|
|
m.d.comb += insn_rem.rvfi_insn.eq(self.rvfi_insn)
|
||
|
|
m.d.comb += insn_rem.rvfi_pc_rdata.eq(self.rvfi_pc_rdata)
|
||
|
|
m.d.comb += insn_rem.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata)
|
||
|
|
m.d.comb += insn_rem.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata)
|
||
|
|
m.d.comb += insn_rem.rvfi_mem_rdata.eq(self.rvfi_mem_rdata)
|
||
|
|
m.d.comb += spec_insn_rem_valid.eq(insn_rem.spec_valid)
|
||
|
|
m.d.comb += spec_insn_rem_trap.eq(insn_rem.spec_trap)
|
||
|
|
m.d.comb += spec_insn_rem_rs1_addr.eq(insn_rem.spec_rs1_addr)
|
||
|
|
m.d.comb += spec_insn_rem_rs2_addr.eq(insn_rem.spec_rs2_addr)
|
||
|
|
m.d.comb += spec_insn_rem_rd_addr.eq(insn_rem.spec_rd_addr)
|
||
|
|
m.d.comb += spec_insn_rem_rd_wdata.eq(insn_rem.spec_rd_wdata)
|
||
|
|
m.d.comb += spec_insn_rem_pc_wdata.eq(insn_rem.spec_pc_wdata)
|
||
|
|
m.d.comb += spec_insn_rem_mem_addr.eq(insn_rem.spec_mem_addr)
|
||
|
|
m.d.comb += spec_insn_rem_mem_rmask.eq(insn_rem.spec_mem_rmask)
|
||
|
|
m.d.comb += spec_insn_rem_mem_wmask.eq(insn_rem.spec_mem_wmask)
|
||
|
|
m.d.comb += spec_insn_rem_mem_wdata.eq(insn_rem.spec_mem_wdata)
|
||
|
|
|
||
|
|
spec_insn_remu_valid = Signal(1)
|
||
|
|
spec_insn_remu_trap = Signal(1)
|
||
|
|
spec_insn_remu_rs1_addr = Signal(5)
|
||
|
|
spec_insn_remu_rs2_addr = Signal(5)
|
||
|
|
spec_insn_remu_rd_addr = Signal(5)
|
||
|
|
spec_insn_remu_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_remu_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_remu_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
spec_insn_remu_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
|
||
|
|
spec_insn_remu_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
|
||
|
|
spec_insn_remu_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||
|
|
m.submodules.insn_remu = insn_remu = rvfi_insn_remu()
|
||
|
|
m.d.comb += insn_remu.rvfi_valid.eq(self.rvfi_valid)
|
||
|
|
m.d.comb += insn_remu.rvfi_insn.eq(self.rvfi_insn)
|
||
|
|
m.d.comb += insn_remu.rvfi_pc_rdata.eq(self.rvfi_pc_rdata)
|
||
|
|
m.d.comb += insn_remu.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata)
|
||
|
|
m.d.comb += insn_remu.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata)
|
||
|
|
m.d.comb += insn_remu.rvfi_mem_rdata.eq(self.rvfi_mem_rdata)
|
||
|
|
m.d.comb += spec_insn_remu_valid.eq(insn_remu.spec_valid)
|
||
|
|
m.d.comb += spec_insn_remu_trap.eq(insn_remu.spec_trap)
|
||
|
|
m.d.comb += spec_insn_remu_rs1_addr.eq(insn_remu.spec_rs1_addr)
|
||
|
|
m.d.comb += spec_insn_remu_rs2_addr.eq(insn_remu.spec_rs2_addr)
|
||
|
|
m.d.comb += spec_insn_remu_rd_addr.eq(insn_remu.spec_rd_addr)
|
||
|
|
m.d.comb += spec_insn_remu_rd_wdata.eq(insn_remu.spec_rd_wdata)
|
||
|
|
m.d.comb += spec_insn_remu_pc_wdata.eq(insn_remu.spec_pc_wdata)
|
||
|
|
m.d.comb += spec_insn_remu_mem_addr.eq(insn_remu.spec_mem_addr)
|
||
|
|
m.d.comb += spec_insn_remu_mem_rmask.eq(insn_remu.spec_mem_rmask)
|
||
|
|
m.d.comb += spec_insn_remu_mem_wmask.eq(insn_remu.spec_mem_wmask)
|
||
|
|
m.d.comb += spec_insn_remu_mem_wdata.eq(insn_remu.spec_mem_wdata)
|
||
|
|
|
||
|
|
m.d.comb += self.spec_valid.eq(Mux(spec_insn_remu_valid, spec_insn_remu_valid, Mux(spec_insn_rem_valid, spec_insn_rem_valid, Mux(spec_insn_divu_valid, spec_insn_divu_valid, Mux(spec_insn_div_valid, spec_insn_div_valid, Mux(spec_insn_mulhu_valid, spec_insn_mulhu_valid, Mux(spec_insn_mulhsu_valid, spec_insn_mulhsu_valid, Mux(spec_insn_mulh_valid, spec_insn_mulh_valid, Mux(spec_insn_mul_valid, spec_insn_mul_valid, Mux(spec_insn_and_valid, spec_insn_and_valid, Mux(spec_insn_or_valid, spec_insn_or_valid, Mux(spec_insn_sra_valid, spec_insn_sra_valid, Mux(spec_insn_srl_valid, spec_insn_srl_valid, Mux(spec_insn_xor_valid, spec_insn_xor_valid, Mux(spec_insn_sltu_valid, spec_insn_sltu_valid, Mux(spec_insn_slt_valid, spec_insn_slt_valid, Mux(spec_insn_sll_valid, spec_insn_sll_valid, Mux(spec_insn_sub_valid, spec_insn_sub_valid, Mux(spec_insn_add_valid, spec_insn_add_valid, Mux(spec_insn_srai_valid, spec_insn_srai_valid, Mux(spec_insn_srli_valid, spec_insn_srli_valid, Mux(spec_insn_slli_valid, spec_insn_slli_valid, Mux(spec_insn_andi_valid, spec_insn_andi_valid, Mux(spec_insn_ori_valid, spec_insn_ori_valid, Mux(spec_insn_xori_valid, spec_insn_xori_valid, Mux(spec_insn_sltiu_valid, spec_insn_sltiu_valid, Mux(spec_insn_slti_valid, spec_insn_slti_valid, Mux(spec_insn_addi_valid, spec_insn_addi_valid, Mux(spec_insn_sw_valid, spec_insn_sw_valid, Mux(spec_insn_sh_valid, spec_insn_sh_valid, Mux(spec_insn_sb_valid, spec_insn_sb_valid, Mux(spec_insn_lhu_valid, spec_insn_lhu_valid, Mux(spec_insn_lbu_valid, spec_insn_lbu_valid, Mux(spec_insn_lw_valid, spec_insn_lw_valid, Mux(spec_insn_lh_valid, spec_insn_lh_valid, Mux(spec_insn_lb_valid, spec_insn_lb_valid, Mux(spec_insn_bgeu_valid, spec_insn_bgeu_valid, Mux(spec_insn_bltu_valid, spec_insn_bltu_valid, Mux(spec_insn_bge_valid, spec_insn_bge_valid, Mux(spec_insn_blt_valid, spec_insn_blt_valid, Mux(spec_insn_bne_valid, spec_insn_bne_valid, Mux(spec_insn_beq_valid, spec_insn_beq_valid, Mux(spec_insn_jalr_valid, spec_insn_jalr_valid, Mux(spec_insn_jal_valid, spec_insn_jal_valid, Mux(spec_insn_auipc_valid, spec_insn_auipc_valid, Mux(spec_insn_lui_valid, spec_insn_lui_valid, 0))))))))))))))))))))))))))))))))))))))))))))))
|
||
|
|
m.d.comb += self.spec_trap.eq(Mux(spec_insn_remu_valid, spec_insn_remu_trap, Mux(spec_insn_rem_valid, spec_insn_rem_trap, Mux(spec_insn_divu_valid, spec_insn_divu_trap, Mux(spec_insn_div_valid, spec_insn_div_trap, Mux(spec_insn_mulhu_valid, spec_insn_mulhu_trap, Mux(spec_insn_mulhsu_valid, spec_insn_mulhsu_trap, Mux(spec_insn_mulh_valid, spec_insn_mulh_trap, Mux(spec_insn_mul_valid, spec_insn_mul_trap, Mux(spec_insn_and_valid, spec_insn_and_trap, Mux(spec_insn_or_valid, spec_insn_or_trap, Mux(spec_insn_sra_valid, spec_insn_sra_trap, Mux(spec_insn_srl_valid, spec_insn_srl_trap, Mux(spec_insn_xor_valid, spec_insn_xor_trap, Mux(spec_insn_sltu_valid, spec_insn_sltu_trap, Mux(spec_insn_slt_valid, spec_insn_slt_trap, Mux(spec_insn_sll_valid, spec_insn_sll_trap, Mux(spec_insn_sub_valid, spec_insn_sub_trap, Mux(spec_insn_add_valid, spec_insn_add_trap, Mux(spec_insn_srai_valid, spec_insn_srai_trap, Mux(spec_insn_srli_valid, spec_insn_srli_trap, Mux(spec_insn_slli_valid, spec_insn_slli_trap, Mux(spec_insn_andi_valid, spec_insn_andi_trap, Mux(spec_insn_ori_valid, spec_insn_ori_trap, Mux(spec_insn_xori_valid, spec_insn_xori_trap, Mux(spec_insn_sltiu_valid, spec_insn_sltiu_trap, Mux(spec_insn_slti_valid, spec_insn_slti_trap, Mux(spec_insn_addi_valid, spec_insn_addi_trap, Mux(spec_insn_sw_valid, spec_insn_sw_trap, Mux(spec_insn_sh_valid, spec_insn_sh_trap, Mux(spec_insn_sb_valid, spec_insn_sb_trap, Mux(spec_insn_lhu_valid, spec_insn_lhu_trap, Mux(spec_insn_lbu_valid, spec_insn_lbu_trap, Mux(spec_insn_lw_valid, spec_insn_lw_trap, Mux(spec_insn_lh_valid, spec_insn_lh_trap, Mux(spec_insn_lb_valid, spec_insn_lb_trap, Mux(spec_insn_bgeu_valid, spec_insn_bgeu_trap, Mux(spec_insn_bltu_valid, spec_insn_bltu_trap, Mux(spec_insn_bge_valid, spec_insn_bge_trap, Mux(spec_insn_blt_valid, spec_insn_blt_trap, Mux(spec_insn_bne_valid, spec_insn_bne_trap, Mux(spec_insn_beq_valid, spec_insn_beq_trap, Mux(spec_insn_jalr_valid, spec_insn_jalr_trap, Mux(spec_insn_jal_valid, spec_insn_jal_trap, Mux(spec_insn_auipc_valid, spec_insn_auipc_trap, Mux(spec_insn_lui_valid, spec_insn_lui_trap, 0))))))))))))))))))))))))))))))))))))))))))))))
|
||
|
|
m.d.comb += self.spec_rs1_addr.eq(Mux(spec_insn_remu_valid, spec_insn_remu_rs1_addr, Mux(spec_insn_rem_valid, spec_insn_rem_rs1_addr, Mux(spec_insn_divu_valid, spec_insn_divu_rs1_addr, Mux(spec_insn_div_valid, spec_insn_div_rs1_addr, Mux(spec_insn_mulhu_valid, spec_insn_mulhu_rs1_addr, Mux(spec_insn_mulhsu_valid, spec_insn_mulhsu_rs1_addr, Mux(spec_insn_mulh_valid, spec_insn_mulh_rs1_addr, Mux(spec_insn_mul_valid, spec_insn_mul_rs1_addr, Mux(spec_insn_and_valid, spec_insn_and_rs1_addr, Mux(spec_insn_or_valid, spec_insn_or_rs1_addr, Mux(spec_insn_sra_valid, spec_insn_sra_rs1_addr, Mux(spec_insn_srl_valid, spec_insn_srl_rs1_addr, Mux(spec_insn_xor_valid, spec_insn_xor_rs1_addr, Mux(spec_insn_sltu_valid, spec_insn_sltu_rs1_addr, Mux(spec_insn_slt_valid, spec_insn_slt_rs1_addr, Mux(spec_insn_sll_valid, spec_insn_sll_rs1_addr, Mux(spec_insn_sub_valid, spec_insn_sub_rs1_addr, Mux(spec_insn_add_valid, spec_insn_add_rs1_addr, Mux(spec_insn_srai_valid, spec_insn_srai_rs1_addr, Mux(spec_insn_srli_valid, spec_insn_srli_rs1_addr, Mux(spec_insn_slli_valid, spec_insn_slli_rs1_addr, Mux(spec_insn_andi_valid, spec_insn_andi_rs1_addr, Mux(spec_insn_ori_valid, spec_insn_ori_rs1_addr, Mux(spec_insn_xori_valid, spec_insn_xori_rs1_addr, Mux(spec_insn_sltiu_valid, spec_insn_sltiu_rs1_addr, Mux(spec_insn_slti_valid, spec_insn_slti_rs1_addr, Mux(spec_insn_addi_valid, spec_insn_addi_rs1_addr, Mux(spec_insn_sw_valid, spec_insn_sw_rs1_addr, Mux(spec_insn_sh_valid, spec_insn_sh_rs1_addr, Mux(spec_insn_sb_valid, spec_insn_sb_rs1_addr, Mux(spec_insn_lhu_valid, spec_insn_lhu_rs1_addr, Mux(spec_insn_lbu_valid, spec_insn_lbu_rs1_addr, Mux(spec_insn_lw_valid, spec_insn_lw_rs1_addr, Mux(spec_insn_lh_valid, spec_insn_lh_rs1_addr, Mux(spec_insn_lb_valid, spec_insn_lb_rs1_addr, Mux(spec_insn_bgeu_valid, spec_insn_bgeu_rs1_addr, Mux(spec_insn_bltu_valid, spec_insn_bltu_rs1_addr, Mux(spec_insn_bge_valid, spec_insn_bge_rs1_addr, Mux(spec_insn_blt_valid, spec_insn_blt_rs1_addr, Mux(spec_insn_bne_valid, spec_insn_bne_rs1_addr, Mux(spec_insn_beq_valid, spec_insn_beq_rs1_addr, Mux(spec_insn_jalr_valid, spec_insn_jalr_rs1_addr, Mux(spec_insn_jal_valid, spec_insn_jal_rs1_addr, Mux(spec_insn_auipc_valid, spec_insn_auipc_rs1_addr, Mux(spec_insn_lui_valid, spec_insn_lui_rs1_addr, 0))))))))))))))))))))))))))))))))))))))))))))))
|
||
|
|
m.d.comb += self.spec_rs2_addr.eq(Mux(spec_insn_remu_valid, spec_insn_remu_rs2_addr, Mux(spec_insn_rem_valid, spec_insn_rem_rs2_addr, Mux(spec_insn_divu_valid, spec_insn_divu_rs2_addr, Mux(spec_insn_div_valid, spec_insn_div_rs2_addr, Mux(spec_insn_mulhu_valid, spec_insn_mulhu_rs2_addr, Mux(spec_insn_mulhsu_valid, spec_insn_mulhsu_rs2_addr, Mux(spec_insn_mulh_valid, spec_insn_mulh_rs2_addr, Mux(spec_insn_mul_valid, spec_insn_mul_rs2_addr, Mux(spec_insn_and_valid, spec_insn_and_rs2_addr, Mux(spec_insn_or_valid, spec_insn_or_rs2_addr, Mux(spec_insn_sra_valid, spec_insn_sra_rs2_addr, Mux(spec_insn_srl_valid, spec_insn_srl_rs2_addr, Mux(spec_insn_xor_valid, spec_insn_xor_rs2_addr, Mux(spec_insn_sltu_valid, spec_insn_sltu_rs2_addr, Mux(spec_insn_slt_valid, spec_insn_slt_rs2_addr, Mux(spec_insn_sll_valid, spec_insn_sll_rs2_addr, Mux(spec_insn_sub_valid, spec_insn_sub_rs2_addr, Mux(spec_insn_add_valid, spec_insn_add_rs2_addr, Mux(spec_insn_srai_valid, spec_insn_srai_rs2_addr, Mux(spec_insn_srli_valid, spec_insn_srli_rs2_addr, Mux(spec_insn_slli_valid, spec_insn_slli_rs2_addr, Mux(spec_insn_andi_valid, spec_insn_andi_rs2_addr, Mux(spec_insn_ori_valid, spec_insn_ori_rs2_addr, Mux(spec_insn_xori_valid, spec_insn_xori_rs2_addr, Mux(spec_insn_sltiu_valid, spec_insn_sltiu_rs2_addr, Mux(spec_insn_slti_valid, spec_insn_slti_rs2_addr, Mux(spec_insn_addi_valid, spec_insn_addi_rs2_addr, Mux(spec_insn_sw_valid, spec_insn_sw_rs2_addr, Mux(spec_insn_sh_valid, spec_insn_sh_rs2_addr, Mux(spec_insn_sb_valid, spec_insn_sb_rs2_addr, Mux(spec_insn_lhu_valid, spec_insn_lhu_rs2_addr, Mux(spec_insn_lbu_valid, spec_insn_lbu_rs2_addr, Mux(spec_insn_lw_valid, spec_insn_lw_rs2_addr, Mux(spec_insn_lh_valid, spec_insn_lh_rs2_addr, Mux(spec_insn_lb_valid, spec_insn_lb_rs2_addr, Mux(spec_insn_bgeu_valid, spec_insn_bgeu_rs2_addr, Mux(spec_insn_bltu_valid, spec_insn_bltu_rs2_addr, Mux(spec_insn_bge_valid, spec_insn_bge_rs2_addr, Mux(spec_insn_blt_valid, spec_insn_blt_rs2_addr, Mux(spec_insn_bne_valid, spec_insn_bne_rs2_addr, Mux(spec_insn_beq_valid, spec_insn_beq_rs2_addr, Mux(spec_insn_jalr_valid, spec_insn_jalr_rs2_addr, Mux(spec_insn_jal_valid, spec_insn_jal_rs2_addr, Mux(spec_insn_auipc_valid, spec_insn_auipc_rs2_addr, Mux(spec_insn_lui_valid, spec_insn_lui_rs2_addr, 0))))))))))))))))))))))))))))))))))))))))))))))
|
||
|
|
m.d.comb += self.spec_rd_addr.eq(Mux(spec_insn_remu_valid, spec_insn_remu_rd_addr, Mux(spec_insn_rem_valid, spec_insn_rem_rd_addr, Mux(spec_insn_divu_valid, spec_insn_divu_rd_addr, Mux(spec_insn_div_valid, spec_insn_div_rd_addr, Mux(spec_insn_mulhu_valid, spec_insn_mulhu_rd_addr, Mux(spec_insn_mulhsu_valid, spec_insn_mulhsu_rd_addr, Mux(spec_insn_mulh_valid, spec_insn_mulh_rd_addr, Mux(spec_insn_mul_valid, spec_insn_mul_rd_addr, Mux(spec_insn_and_valid, spec_insn_and_rd_addr, Mux(spec_insn_or_valid, spec_insn_or_rd_addr, Mux(spec_insn_sra_valid, spec_insn_sra_rd_addr, Mux(spec_insn_srl_valid, spec_insn_srl_rd_addr, Mux(spec_insn_xor_valid, spec_insn_xor_rd_addr, Mux(spec_insn_sltu_valid, spec_insn_sltu_rd_addr, Mux(spec_insn_slt_valid, spec_insn_slt_rd_addr, Mux(spec_insn_sll_valid, spec_insn_sll_rd_addr, Mux(spec_insn_sub_valid, spec_insn_sub_rd_addr, Mux(spec_insn_add_valid, spec_insn_add_rd_addr, Mux(spec_insn_srai_valid, spec_insn_srai_rd_addr, Mux(spec_insn_srli_valid, spec_insn_srli_rd_addr, Mux(spec_insn_slli_valid, spec_insn_slli_rd_addr, Mux(spec_insn_andi_valid, spec_insn_andi_rd_addr, Mux(spec_insn_ori_valid, spec_insn_ori_rd_addr, Mux(spec_insn_xori_valid, spec_insn_xori_rd_addr, Mux(spec_insn_sltiu_valid, spec_insn_sltiu_rd_addr, Mux(spec_insn_slti_valid, spec_insn_slti_rd_addr, Mux(spec_insn_addi_valid, spec_insn_addi_rd_addr, Mux(spec_insn_sw_valid, spec_insn_sw_rd_addr, Mux(spec_insn_sh_valid, spec_insn_sh_rd_addr, Mux(spec_insn_sb_valid, spec_insn_sb_rd_addr, Mux(spec_insn_lhu_valid, spec_insn_lhu_rd_addr, Mux(spec_insn_lbu_valid, spec_insn_lbu_rd_addr, Mux(spec_insn_lw_valid, spec_insn_lw_rd_addr, Mux(spec_insn_lh_valid, spec_insn_lh_rd_addr, Mux(spec_insn_lb_valid, spec_insn_lb_rd_addr, Mux(spec_insn_bgeu_valid, spec_insn_bgeu_rd_addr, Mux(spec_insn_bltu_valid, spec_insn_bltu_rd_addr, Mux(spec_insn_bge_valid, spec_insn_bge_rd_addr, Mux(spec_insn_blt_valid, spec_insn_blt_rd_addr, Mux(spec_insn_bne_valid, spec_insn_bne_rd_addr, Mux(spec_insn_beq_valid, spec_insn_beq_rd_addr, Mux(spec_insn_jalr_valid, spec_insn_jalr_rd_addr, Mux(spec_insn_jal_valid, spec_insn_jal_rd_addr, Mux(spec_insn_auipc_valid, spec_insn_auipc_rd_addr, Mux(spec_insn_lui_valid, spec_insn_lui_rd_addr, 0))))))))))))))))))))))))))))))))))))))))))))))
|
||
|
|
m.d.comb += self.spec_rd_wdata.eq(Mux(spec_insn_remu_valid, spec_insn_remu_rd_wdata, Mux(spec_insn_rem_valid, spec_insn_rem_rd_wdata, Mux(spec_insn_divu_valid, spec_insn_divu_rd_wdata, Mux(spec_insn_div_valid, spec_insn_div_rd_wdata, Mux(spec_insn_mulhu_valid, spec_insn_mulhu_rd_wdata, Mux(spec_insn_mulhsu_valid, spec_insn_mulhsu_rd_wdata, Mux(spec_insn_mulh_valid, spec_insn_mulh_rd_wdata, Mux(spec_insn_mul_valid, spec_insn_mul_rd_wdata, Mux(spec_insn_and_valid, spec_insn_and_rd_wdata, Mux(spec_insn_or_valid, spec_insn_or_rd_wdata, Mux(spec_insn_sra_valid, spec_insn_sra_rd_wdata, Mux(spec_insn_srl_valid, spec_insn_srl_rd_wdata, Mux(spec_insn_xor_valid, spec_insn_xor_rd_wdata, Mux(spec_insn_sltu_valid, spec_insn_sltu_rd_wdata, Mux(spec_insn_slt_valid, spec_insn_slt_rd_wdata, Mux(spec_insn_sll_valid, spec_insn_sll_rd_wdata, Mux(spec_insn_sub_valid, spec_insn_sub_rd_wdata, Mux(spec_insn_add_valid, spec_insn_add_rd_wdata, Mux(spec_insn_srai_valid, spec_insn_srai_rd_wdata, Mux(spec_insn_srli_valid, spec_insn_srli_rd_wdata, Mux(spec_insn_slli_valid, spec_insn_slli_rd_wdata, Mux(spec_insn_andi_valid, spec_insn_andi_rd_wdata, Mux(spec_insn_ori_valid, spec_insn_ori_rd_wdata, Mux(spec_insn_xori_valid, spec_insn_xori_rd_wdata, Mux(spec_insn_sltiu_valid, spec_insn_sltiu_rd_wdata, Mux(spec_insn_slti_valid, spec_insn_slti_rd_wdata, Mux(spec_insn_addi_valid, spec_insn_addi_rd_wdata, Mux(spec_insn_sw_valid, spec_insn_sw_rd_wdata, Mux(spec_insn_sh_valid, spec_insn_sh_rd_wdata, Mux(spec_insn_sb_valid, spec_insn_sb_rd_wdata, Mux(spec_insn_lhu_valid, spec_insn_lhu_rd_wdata, Mux(spec_insn_lbu_valid, spec_insn_lbu_rd_wdata, Mux(spec_insn_lw_valid, spec_insn_lw_rd_wdata, Mux(spec_insn_lh_valid, spec_insn_lh_rd_wdata, Mux(spec_insn_lb_valid, spec_insn_lb_rd_wdata, Mux(spec_insn_bgeu_valid, spec_insn_bgeu_rd_wdata, Mux(spec_insn_bltu_valid, spec_insn_bltu_rd_wdata, Mux(spec_insn_bge_valid, spec_insn_bge_rd_wdata, Mux(spec_insn_blt_valid, spec_insn_blt_rd_wdata, Mux(spec_insn_bne_valid, spec_insn_bne_rd_wdata, Mux(spec_insn_beq_valid, spec_insn_beq_rd_wdata, Mux(spec_insn_jalr_valid, spec_insn_jalr_rd_wdata, Mux(spec_insn_jal_valid, spec_insn_jal_rd_wdata, Mux(spec_insn_auipc_valid, spec_insn_auipc_rd_wdata, Mux(spec_insn_lui_valid, spec_insn_lui_rd_wdata, 0))))))))))))))))))))))))))))))))))))))))))))))
|
||
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|
m.d.comb += self.spec_pc_wdata.eq(Mux(spec_insn_remu_valid, spec_insn_remu_pc_wdata, Mux(spec_insn_rem_valid, spec_insn_rem_pc_wdata, Mux(spec_insn_divu_valid, spec_insn_divu_pc_wdata, Mux(spec_insn_div_valid, spec_insn_div_pc_wdata, Mux(spec_insn_mulhu_valid, spec_insn_mulhu_pc_wdata, Mux(spec_insn_mulhsu_valid, spec_insn_mulhsu_pc_wdata, Mux(spec_insn_mulh_valid, spec_insn_mulh_pc_wdata, Mux(spec_insn_mul_valid, spec_insn_mul_pc_wdata, Mux(spec_insn_and_valid, spec_insn_and_pc_wdata, Mux(spec_insn_or_valid, spec_insn_or_pc_wdata, Mux(spec_insn_sra_valid, spec_insn_sra_pc_wdata, Mux(spec_insn_srl_valid, spec_insn_srl_pc_wdata, Mux(spec_insn_xor_valid, spec_insn_xor_pc_wdata, Mux(spec_insn_sltu_valid, spec_insn_sltu_pc_wdata, Mux(spec_insn_slt_valid, spec_insn_slt_pc_wdata, Mux(spec_insn_sll_valid, spec_insn_sll_pc_wdata, Mux(spec_insn_sub_valid, spec_insn_sub_pc_wdata, Mux(spec_insn_add_valid, spec_insn_add_pc_wdata, Mux(spec_insn_srai_valid, spec_insn_srai_pc_wdata, Mux(spec_insn_srli_valid, spec_insn_srli_pc_wdata, Mux(spec_insn_slli_valid, spec_insn_slli_pc_wdata, Mux(spec_insn_andi_valid, spec_insn_andi_pc_wdata, Mux(spec_insn_ori_valid, spec_insn_ori_pc_wdata, Mux(spec_insn_xori_valid, spec_insn_xori_pc_wdata, Mux(spec_insn_sltiu_valid, spec_insn_sltiu_pc_wdata, Mux(spec_insn_slti_valid, spec_insn_slti_pc_wdata, Mux(spec_insn_addi_valid, spec_insn_addi_pc_wdata, Mux(spec_insn_sw_valid, spec_insn_sw_pc_wdata, Mux(spec_insn_sh_valid, spec_insn_sh_pc_wdata, Mux(spec_insn_sb_valid, spec_insn_sb_pc_wdata, Mux(spec_insn_lhu_valid, spec_insn_lhu_pc_wdata, Mux(spec_insn_lbu_valid, spec_insn_lbu_pc_wdata, Mux(spec_insn_lw_valid, spec_insn_lw_pc_wdata, Mux(spec_insn_lh_valid, spec_insn_lh_pc_wdata, Mux(spec_insn_lb_valid, spec_insn_lb_pc_wdata, Mux(spec_insn_bgeu_valid, spec_insn_bgeu_pc_wdata, Mux(spec_insn_bltu_valid, spec_insn_bltu_pc_wdata, Mux(spec_insn_bge_valid, spec_insn_bge_pc_wdata, Mux(spec_insn_blt_valid, spec_insn_blt_pc_wdata, Mux(spec_insn_bne_valid, spec_insn_bne_pc_wdata, Mux(spec_insn_beq_valid, spec_insn_beq_pc_wdata, Mux(spec_insn_jalr_valid, spec_insn_jalr_pc_wdata, Mux(spec_insn_jal_valid, spec_insn_jal_pc_wdata, Mux(spec_insn_auipc_valid, spec_insn_auipc_pc_wdata, Mux(spec_insn_lui_valid, spec_insn_lui_pc_wdata, 0))))))))))))))))))))))))))))))))))))))))))))))
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||
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m.d.comb += self.spec_mem_addr.eq(Mux(spec_insn_remu_valid, spec_insn_remu_mem_addr, Mux(spec_insn_rem_valid, spec_insn_rem_mem_addr, Mux(spec_insn_divu_valid, spec_insn_divu_mem_addr, Mux(spec_insn_div_valid, spec_insn_div_mem_addr, Mux(spec_insn_mulhu_valid, spec_insn_mulhu_mem_addr, Mux(spec_insn_mulhsu_valid, spec_insn_mulhsu_mem_addr, Mux(spec_insn_mulh_valid, spec_insn_mulh_mem_addr, Mux(spec_insn_mul_valid, spec_insn_mul_mem_addr, Mux(spec_insn_and_valid, spec_insn_and_mem_addr, Mux(spec_insn_or_valid, spec_insn_or_mem_addr, Mux(spec_insn_sra_valid, spec_insn_sra_mem_addr, Mux(spec_insn_srl_valid, spec_insn_srl_mem_addr, Mux(spec_insn_xor_valid, spec_insn_xor_mem_addr, Mux(spec_insn_sltu_valid, spec_insn_sltu_mem_addr, Mux(spec_insn_slt_valid, spec_insn_slt_mem_addr, Mux(spec_insn_sll_valid, spec_insn_sll_mem_addr, Mux(spec_insn_sub_valid, spec_insn_sub_mem_addr, Mux(spec_insn_add_valid, spec_insn_add_mem_addr, Mux(spec_insn_srai_valid, spec_insn_srai_mem_addr, Mux(spec_insn_srli_valid, spec_insn_srli_mem_addr, Mux(spec_insn_slli_valid, spec_insn_slli_mem_addr, Mux(spec_insn_andi_valid, spec_insn_andi_mem_addr, Mux(spec_insn_ori_valid, spec_insn_ori_mem_addr, Mux(spec_insn_xori_valid, spec_insn_xori_mem_addr, Mux(spec_insn_sltiu_valid, spec_insn_sltiu_mem_addr, Mux(spec_insn_slti_valid, spec_insn_slti_mem_addr, Mux(spec_insn_addi_valid, spec_insn_addi_mem_addr, Mux(spec_insn_sw_valid, spec_insn_sw_mem_addr, Mux(spec_insn_sh_valid, spec_insn_sh_mem_addr, Mux(spec_insn_sb_valid, spec_insn_sb_mem_addr, Mux(spec_insn_lhu_valid, spec_insn_lhu_mem_addr, Mux(spec_insn_lbu_valid, spec_insn_lbu_mem_addr, Mux(spec_insn_lw_valid, spec_insn_lw_mem_addr, Mux(spec_insn_lh_valid, spec_insn_lh_mem_addr, Mux(spec_insn_lb_valid, spec_insn_lb_mem_addr, Mux(spec_insn_bgeu_valid, spec_insn_bgeu_mem_addr, Mux(spec_insn_bltu_valid, spec_insn_bltu_mem_addr, Mux(spec_insn_bge_valid, spec_insn_bge_mem_addr, Mux(spec_insn_blt_valid, spec_insn_blt_mem_addr, Mux(spec_insn_bne_valid, spec_insn_bne_mem_addr, Mux(spec_insn_beq_valid, spec_insn_beq_mem_addr, Mux(spec_insn_jalr_valid, spec_insn_jalr_mem_addr, Mux(spec_insn_jal_valid, spec_insn_jal_mem_addr, Mux(spec_insn_auipc_valid, spec_insn_auipc_mem_addr, Mux(spec_insn_lui_valid, spec_insn_lui_mem_addr, 0))))))))))))))))))))))))))))))))))))))))))))))
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||
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m.d.comb += self.spec_mem_rmask.eq(Mux(spec_insn_remu_valid, spec_insn_remu_mem_rmask, Mux(spec_insn_rem_valid, spec_insn_rem_mem_rmask, Mux(spec_insn_divu_valid, spec_insn_divu_mem_rmask, Mux(spec_insn_div_valid, spec_insn_div_mem_rmask, Mux(spec_insn_mulhu_valid, spec_insn_mulhu_mem_rmask, Mux(spec_insn_mulhsu_valid, spec_insn_mulhsu_mem_rmask, Mux(spec_insn_mulh_valid, spec_insn_mulh_mem_rmask, Mux(spec_insn_mul_valid, spec_insn_mul_mem_rmask, Mux(spec_insn_and_valid, spec_insn_and_mem_rmask, Mux(spec_insn_or_valid, spec_insn_or_mem_rmask, Mux(spec_insn_sra_valid, spec_insn_sra_mem_rmask, Mux(spec_insn_srl_valid, spec_insn_srl_mem_rmask, Mux(spec_insn_xor_valid, spec_insn_xor_mem_rmask, Mux(spec_insn_sltu_valid, spec_insn_sltu_mem_rmask, Mux(spec_insn_slt_valid, spec_insn_slt_mem_rmask, Mux(spec_insn_sll_valid, spec_insn_sll_mem_rmask, Mux(spec_insn_sub_valid, spec_insn_sub_mem_rmask, Mux(spec_insn_add_valid, spec_insn_add_mem_rmask, Mux(spec_insn_srai_valid, spec_insn_srai_mem_rmask, Mux(spec_insn_srli_valid, spec_insn_srli_mem_rmask, Mux(spec_insn_slli_valid, spec_insn_slli_mem_rmask, Mux(spec_insn_andi_valid, spec_insn_andi_mem_rmask, Mux(spec_insn_ori_valid, spec_insn_ori_mem_rmask, Mux(spec_insn_xori_valid, spec_insn_xori_mem_rmask, Mux(spec_insn_sltiu_valid, spec_insn_sltiu_mem_rmask, Mux(spec_insn_slti_valid, spec_insn_slti_mem_rmask, Mux(spec_insn_addi_valid, spec_insn_addi_mem_rmask, Mux(spec_insn_sw_valid, spec_insn_sw_mem_rmask, Mux(spec_insn_sh_valid, spec_insn_sh_mem_rmask, Mux(spec_insn_sb_valid, spec_insn_sb_mem_rmask, Mux(spec_insn_lhu_valid, spec_insn_lhu_mem_rmask, Mux(spec_insn_lbu_valid, spec_insn_lbu_mem_rmask, Mux(spec_insn_lw_valid, spec_insn_lw_mem_rmask, Mux(spec_insn_lh_valid, spec_insn_lh_mem_rmask, Mux(spec_insn_lb_valid, spec_insn_lb_mem_rmask, Mux(spec_insn_bgeu_valid, spec_insn_bgeu_mem_rmask, Mux(spec_insn_bltu_valid, spec_insn_bltu_mem_rmask, Mux(spec_insn_bge_valid, spec_insn_bge_mem_rmask, Mux(spec_insn_blt_valid, spec_insn_blt_mem_rmask, Mux(spec_insn_bne_valid, spec_insn_bne_mem_rmask, Mux(spec_insn_beq_valid, spec_insn_beq_mem_rmask, Mux(spec_insn_jalr_valid, spec_insn_jalr_mem_rmask, Mux(spec_insn_jal_valid, spec_insn_jal_mem_rmask, Mux(spec_insn_auipc_valid, spec_insn_auipc_mem_rmask, Mux(spec_insn_lui_valid, spec_insn_lui_mem_rmask, 0))))))))))))))))))))))))))))))))))))))))))))))
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||
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m.d.comb += self.spec_mem_wmask.eq(Mux(spec_insn_remu_valid, spec_insn_remu_mem_wmask, Mux(spec_insn_rem_valid, spec_insn_rem_mem_wmask, Mux(spec_insn_divu_valid, spec_insn_divu_mem_wmask, Mux(spec_insn_div_valid, spec_insn_div_mem_wmask, Mux(spec_insn_mulhu_valid, spec_insn_mulhu_mem_wmask, Mux(spec_insn_mulhsu_valid, spec_insn_mulhsu_mem_wmask, Mux(spec_insn_mulh_valid, spec_insn_mulh_mem_wmask, Mux(spec_insn_mul_valid, spec_insn_mul_mem_wmask, Mux(spec_insn_and_valid, spec_insn_and_mem_wmask, Mux(spec_insn_or_valid, spec_insn_or_mem_wmask, Mux(spec_insn_sra_valid, spec_insn_sra_mem_wmask, Mux(spec_insn_srl_valid, spec_insn_srl_mem_wmask, Mux(spec_insn_xor_valid, spec_insn_xor_mem_wmask, Mux(spec_insn_sltu_valid, spec_insn_sltu_mem_wmask, Mux(spec_insn_slt_valid, spec_insn_slt_mem_wmask, Mux(spec_insn_sll_valid, spec_insn_sll_mem_wmask, Mux(spec_insn_sub_valid, spec_insn_sub_mem_wmask, Mux(spec_insn_add_valid, spec_insn_add_mem_wmask, Mux(spec_insn_srai_valid, spec_insn_srai_mem_wmask, Mux(spec_insn_srli_valid, spec_insn_srli_mem_wmask, Mux(spec_insn_slli_valid, spec_insn_slli_mem_wmask, Mux(spec_insn_andi_valid, spec_insn_andi_mem_wmask, Mux(spec_insn_ori_valid, spec_insn_ori_mem_wmask, Mux(spec_insn_xori_valid, spec_insn_xori_mem_wmask, Mux(spec_insn_sltiu_valid, spec_insn_sltiu_mem_wmask, Mux(spec_insn_slti_valid, spec_insn_slti_mem_wmask, Mux(spec_insn_addi_valid, spec_insn_addi_mem_wmask, Mux(spec_insn_sw_valid, spec_insn_sw_mem_wmask, Mux(spec_insn_sh_valid, spec_insn_sh_mem_wmask, Mux(spec_insn_sb_valid, spec_insn_sb_mem_wmask, Mux(spec_insn_lhu_valid, spec_insn_lhu_mem_wmask, Mux(spec_insn_lbu_valid, spec_insn_lbu_mem_wmask, Mux(spec_insn_lw_valid, spec_insn_lw_mem_wmask, Mux(spec_insn_lh_valid, spec_insn_lh_mem_wmask, Mux(spec_insn_lb_valid, spec_insn_lb_mem_wmask, Mux(spec_insn_bgeu_valid, spec_insn_bgeu_mem_wmask, Mux(spec_insn_bltu_valid, spec_insn_bltu_mem_wmask, Mux(spec_insn_bge_valid, spec_insn_bge_mem_wmask, Mux(spec_insn_blt_valid, spec_insn_blt_mem_wmask, Mux(spec_insn_bne_valid, spec_insn_bne_mem_wmask, Mux(spec_insn_beq_valid, spec_insn_beq_mem_wmask, Mux(spec_insn_jalr_valid, spec_insn_jalr_mem_wmask, Mux(spec_insn_jal_valid, spec_insn_jal_mem_wmask, Mux(spec_insn_auipc_valid, spec_insn_auipc_mem_wmask, Mux(spec_insn_lui_valid, spec_insn_lui_mem_wmask, 0))))))))))))))))))))))))))))))))))))))))))))))
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||
|
|
m.d.comb += self.spec_mem_wdata.eq(Mux(spec_insn_remu_valid, spec_insn_remu_mem_wdata, Mux(spec_insn_rem_valid, spec_insn_rem_mem_wdata, Mux(spec_insn_divu_valid, spec_insn_divu_mem_wdata, Mux(spec_insn_div_valid, spec_insn_div_mem_wdata, Mux(spec_insn_mulhu_valid, spec_insn_mulhu_mem_wdata, Mux(spec_insn_mulhsu_valid, spec_insn_mulhsu_mem_wdata, Mux(spec_insn_mulh_valid, spec_insn_mulh_mem_wdata, Mux(spec_insn_mul_valid, spec_insn_mul_mem_wdata, Mux(spec_insn_and_valid, spec_insn_and_mem_wdata, Mux(spec_insn_or_valid, spec_insn_or_mem_wdata, Mux(spec_insn_sra_valid, spec_insn_sra_mem_wdata, Mux(spec_insn_srl_valid, spec_insn_srl_mem_wdata, Mux(spec_insn_xor_valid, spec_insn_xor_mem_wdata, Mux(spec_insn_sltu_valid, spec_insn_sltu_mem_wdata, Mux(spec_insn_slt_valid, spec_insn_slt_mem_wdata, Mux(spec_insn_sll_valid, spec_insn_sll_mem_wdata, Mux(spec_insn_sub_valid, spec_insn_sub_mem_wdata, Mux(spec_insn_add_valid, spec_insn_add_mem_wdata, Mux(spec_insn_srai_valid, spec_insn_srai_mem_wdata, Mux(spec_insn_srli_valid, spec_insn_srli_mem_wdata, Mux(spec_insn_slli_valid, spec_insn_slli_mem_wdata, Mux(spec_insn_andi_valid, spec_insn_andi_mem_wdata, Mux(spec_insn_ori_valid, spec_insn_ori_mem_wdata, Mux(spec_insn_xori_valid, spec_insn_xori_mem_wdata, Mux(spec_insn_sltiu_valid, spec_insn_sltiu_mem_wdata, Mux(spec_insn_slti_valid, spec_insn_slti_mem_wdata, Mux(spec_insn_addi_valid, spec_insn_addi_mem_wdata, Mux(spec_insn_sw_valid, spec_insn_sw_mem_wdata, Mux(spec_insn_sh_valid, spec_insn_sh_mem_wdata, Mux(spec_insn_sb_valid, spec_insn_sb_mem_wdata, Mux(spec_insn_lhu_valid, spec_insn_lhu_mem_wdata, Mux(spec_insn_lbu_valid, spec_insn_lbu_mem_wdata, Mux(spec_insn_lw_valid, spec_insn_lw_mem_wdata, Mux(spec_insn_lh_valid, spec_insn_lh_mem_wdata, Mux(spec_insn_lb_valid, spec_insn_lb_mem_wdata, Mux(spec_insn_bgeu_valid, spec_insn_bgeu_mem_wdata, Mux(spec_insn_bltu_valid, spec_insn_bltu_mem_wdata, Mux(spec_insn_bge_valid, spec_insn_bge_mem_wdata, Mux(spec_insn_blt_valid, spec_insn_blt_mem_wdata, Mux(spec_insn_bne_valid, spec_insn_bne_mem_wdata, Mux(spec_insn_beq_valid, spec_insn_beq_mem_wdata, Mux(spec_insn_jalr_valid, spec_insn_jalr_mem_wdata, Mux(spec_insn_jal_valid, spec_insn_jal_mem_wdata, Mux(spec_insn_auipc_valid, spec_insn_auipc_mem_wdata, Mux(spec_insn_lui_valid, spec_insn_lui_mem_wdata, 0))))))))))))))))))))))))))))))))))))))))))))))
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return m
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