39 lines
1.4 KiB
Python
39 lines
1.4 KiB
Python
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from insn import *
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class rvfi_insn_SB(rvfi_insn):
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def __init__(self):
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super(rvfi_insn_SB, self).__init__()
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self.insn_padding = Signal(32)
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self.insn_imm = Signal(32)
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self.insn_rs2 = Signal(5)
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self.insn_rs1 = Signal(5)
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self.insn_funct3 = Signal(3)
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self.insn_opcode = Signal(7)
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self.misa_ok = Signal(1)
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self.ialign16 = Signal(1)
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def ports(self):
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return super(rvfi_insn_SB, self).ports()
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def elaborate(self, platform):
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m = super(rvfi_insn_SB, self).elaborate(platform)
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# SB-type instruction format
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m.d.comb += self.insn_padding.eq(self.rvfi_insn >> 32)
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m.d.comb += self.insn_imm.eq(Value.as_signed(Cat(self.rvfi_insn[8:12], self.rvfi_insn[25:31], self.rvfi_insn[7], self.rvfi_insn[31]) << 1))
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m.d.comb += self.insn_rs2.eq(self.rvfi_insn[20:25])
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m.d.comb += self.insn_rs1.eq(self.rvfi_insn[15:20])
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m.d.comb += self.insn_funct3.eq(self.rvfi_insn[12:15])
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m.d.comb += self.insn_opcode.eq(self.rvfi_insn[:7])
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m.d.comb += self.misa_ok.eq(1)
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m.d.comb += self.ialign16.eq(0)
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# default assignments
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m.d.comb += self.spec_rd_addr.eq(0)
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m.d.comb += self.spec_rd_wdata.eq(0)
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m.d.comb += self.spec_mem_addr.eq(0)
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m.d.comb += self.spec_mem_rmask.eq(0)
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m.d.comb += self.spec_mem_wmask.eq(0)
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m.d.comb += self.spec_mem_wdata.eq(0)
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return m
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