83 lines
3.2 KiB
Python
83 lines
3.2 KiB
Python
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from nmigen import *
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from nmigen.hdl.ast import *
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class rvfi_dmem_check(Elaboratable):
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def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
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self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
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self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
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self.reset = Signal(1)
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self.enable = Signal(1)
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self.dmem_addr = Signal(self.RISCV_FORMAL_XLEN)
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self.rvfi_valid = Signal(1)
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self.rvfi_order = Signal(64)
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self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
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self.rvfi_trap = Signal(1)
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self.rvfi_halt = Signal(1)
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self.rvfi_intr = Signal(1)
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self.rvfi_mode = Signal(2)
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self.rvfi_ixl = Signal(2)
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self.rvfi_rs1_addr = Signal(5)
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self.rvfi_rs2_addr = Signal(5)
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self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
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self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
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self.rvfi_rd_addr = Signal(5)
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self.rvfi_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
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self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
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self.rvfi_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
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self.rvfi_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
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self.rvfi_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
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self.rvfi_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
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self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
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self.rvfi_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
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def ports(self):
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input_ports = [
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self.reset,
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self.enable,
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self.rvfi_valid,
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self.rvfi_order,
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self.rvfi_insn,
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self.rvfi_trap,
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self.rvfi_halt,
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self.rvfi_intr,
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self.rvfi_mode,
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self.rvfi_ixl,
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self.rvfi_rs1_addr,
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self.rvfi_rs2_addr,
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self.rvfi_rs1_rdata,
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self.rvfi_rs2_rdata,
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self.rvfi_rd_addr,
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self.rvfi_rd_wdata,
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self.rvfi_pc_rdata,
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self.rvfi_pc_wdata,
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self.rvfi_mem_addr,
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self.rvfi_mem_rmask,
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self.rvfi_mem_wmask,
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self.rvfi_mem_rdata,
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self.rvfi_mem_wdata
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]
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output_ports = [
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self.dmem_addr
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]
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return input_ports + output_ports
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def elaborate(self, platform):
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m = Module()
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dmem_addr_randval = AnyConst(self.RISCV_FORMAL_XLEN)
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m.d.comb += self.dmem_addr.eq(dmem_addr_randval)
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dmem_shadow = Signal(self.RISCV_FORMAL_XLEN)
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dmem_written = Signal(int(self.RISCV_FORMAL_XLEN // 8), reset=0)
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with m.If(self.reset):
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m.d.sync += dmem_written.eq(0)
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with m.Else():
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with m.If(self.rvfi_valid & (self.rvfi_mem_addr == self.dmem_addr) & 1):
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for i in range(int(self.RISCV_FORMAL_XLEN // 8)):
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with m.If(self.enable & self.rvfi_mem_rmask[i] & dmem_written[i]):
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m.d.comb += Assert(dmem_shadow[i*8:i*8+8] == self.rvfi_mem_rdata[i*8:i*8+8])
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with m.If(self.rvfi_mem_wmask[i]):
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m.d.sync += dmem_shadow[i*8:i*8+8].eq(self.rvfi_mem_wdata[i*8:i*8+8])
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m.d.sync += dmem_written[i].eq(1)
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return m
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