44 lines
1.1 KiB
Python
44 lines
1.1 KiB
Python
|
from nmigen import *
|
||
|
from nmigen.asserts import *
|
||
|
|
||
|
"""
|
||
|
Unique Check
|
||
|
"""
|
||
|
|
||
|
class UniqueCheck(Elaboratable):
|
||
|
def __init__(self):
|
||
|
self.reset = Signal(1)
|
||
|
self.rvfi_valid = Signal(1)
|
||
|
self.rvfi_order = Signal(64)
|
||
|
self.trig = Signal(1)
|
||
|
self.check = Signal(1)
|
||
|
|
||
|
def ports(self):
|
||
|
input_ports = [
|
||
|
self.reset,
|
||
|
self.rvfi_valid,
|
||
|
self.rvfi_order,
|
||
|
self.trig,
|
||
|
self.check
|
||
|
]
|
||
|
return input_ports
|
||
|
|
||
|
def elaborate(self, platform):
|
||
|
m = Module()
|
||
|
|
||
|
insn_order = AnyConst(64)
|
||
|
found_other_insn = Signal(1, reset=0)
|
||
|
|
||
|
with m.If(self.reset):
|
||
|
m.d.sync += found_other_insn.eq(0)
|
||
|
with m.Else():
|
||
|
with m.If(self.rvfi_valid & (self.rvfi_order == insn_order) & ~self.trig):
|
||
|
m.d.sync += found_other_insn.eq(1)
|
||
|
with m.If(self.trig):
|
||
|
m.d.comb += Assume(self.rvfi_valid)
|
||
|
m.d.comb += Assume(insn_order == self.rvfi_order)
|
||
|
with m.If(self.check):
|
||
|
m.d.comb += Assert(~found_other_insn)
|
||
|
|
||
|
return m
|