727 lines
27 KiB
Python
727 lines
27 KiB
Python
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import os
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from contextlib import contextmanager
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from .utils import *
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from .._utils import flatten, union
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from ..hdl.ast import *
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from ..hdl.cd import *
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from ..hdl.mem import *
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from ..hdl.rec import *
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from ..hdl.dsl import *
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from ..hdl.ir import *
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from ..back.pysim import *
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class SimulatorUnitTestCase(FHDLTestCase):
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def assertStatement(self, stmt, inputs, output, reset=0):
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inputs = [Value.cast(i) for i in inputs]
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output = Value.cast(output)
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isigs = [Signal(i.shape(), name=n) for i, n in zip(inputs, "abcd")]
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osig = Signal(output.shape(), name="y", reset=reset)
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stmt = stmt(osig, *isigs)
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frag = Fragment()
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frag.add_statements(stmt)
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for signal in flatten(s._lhs_signals() for s in Statement.cast(stmt)):
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frag.add_driver(signal)
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sim = Simulator(frag)
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def process():
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for isig, input in zip(isigs, inputs):
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yield isig.eq(input)
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yield Settle()
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self.assertEqual((yield osig), output.value)
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sim.add_process(process)
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with sim.write_vcd("test.vcd", "test.gtkw", traces=[*isigs, osig]):
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sim.run()
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def test_invert(self):
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stmt = lambda y, a: y.eq(~a)
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self.assertStatement(stmt, [C(0b0000, 4)], C(0b1111, 4))
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self.assertStatement(stmt, [C(0b1010, 4)], C(0b0101, 4))
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self.assertStatement(stmt, [C(0, 4)], C(-1, 4))
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def test_neg(self):
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stmt = lambda y, a: y.eq(-a)
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self.assertStatement(stmt, [C(0b0000, 4)], C(0b0000, 4))
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self.assertStatement(stmt, [C(0b0001, 4)], C(0b1111, 4))
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self.assertStatement(stmt, [C(0b1010, 4)], C(0b0110, 4))
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self.assertStatement(stmt, [C(1, 4)], C(-1, 4))
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self.assertStatement(stmt, [C(5, 4)], C(-5, 4))
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def test_bool(self):
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stmt = lambda y, a: y.eq(a.bool())
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self.assertStatement(stmt, [C(0, 4)], C(0))
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self.assertStatement(stmt, [C(1, 4)], C(1))
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self.assertStatement(stmt, [C(2, 4)], C(1))
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def test_as_unsigned(self):
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stmt = lambda y, a, b: y.eq(a.as_unsigned() == b)
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self.assertStatement(stmt, [C(0b01, signed(2)), C(0b0001, unsigned(4))], C(1))
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self.assertStatement(stmt, [C(0b11, signed(2)), C(0b0011, unsigned(4))], C(1))
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def test_as_signed(self):
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stmt = lambda y, a, b: y.eq(a.as_signed() == b)
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self.assertStatement(stmt, [C(0b01, unsigned(2)), C(0b0001, signed(4))], C(1))
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self.assertStatement(stmt, [C(0b11, unsigned(2)), C(0b1111, signed(4))], C(1))
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def test_any(self):
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stmt = lambda y, a: y.eq(a.any())
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self.assertStatement(stmt, [C(0b00, 2)], C(0))
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self.assertStatement(stmt, [C(0b01, 2)], C(1))
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self.assertStatement(stmt, [C(0b10, 2)], C(1))
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self.assertStatement(stmt, [C(0b11, 2)], C(1))
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def test_all(self):
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stmt = lambda y, a: y.eq(a.all())
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self.assertStatement(stmt, [C(0b00, 2)], C(0))
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self.assertStatement(stmt, [C(0b01, 2)], C(0))
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self.assertStatement(stmt, [C(0b10, 2)], C(0))
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self.assertStatement(stmt, [C(0b11, 2)], C(1))
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def test_xor_unary(self):
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stmt = lambda y, a: y.eq(a.xor())
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self.assertStatement(stmt, [C(0b00, 2)], C(0))
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self.assertStatement(stmt, [C(0b01, 2)], C(1))
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self.assertStatement(stmt, [C(0b10, 2)], C(1))
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self.assertStatement(stmt, [C(0b11, 2)], C(0))
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def test_add(self):
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stmt = lambda y, a, b: y.eq(a + b)
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self.assertStatement(stmt, [C(0, 4), C(1, 4)], C(1, 4))
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self.assertStatement(stmt, [C(-5, 4), C(-5, 4)], C(-10, 5))
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def test_sub(self):
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stmt = lambda y, a, b: y.eq(a - b)
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self.assertStatement(stmt, [C(2, 4), C(1, 4)], C(1, 4))
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self.assertStatement(stmt, [C(0, 4), C(1, 4)], C(-1, 4))
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self.assertStatement(stmt, [C(0, 4), C(10, 4)], C(-10, 5))
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def test_mul(self):
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stmt = lambda y, a, b: y.eq(a * b)
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self.assertStatement(stmt, [C(2, 4), C(1, 4)], C(2, 8))
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self.assertStatement(stmt, [C(2, 4), C(2, 4)], C(4, 8))
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self.assertStatement(stmt, [C(7, 4), C(7, 4)], C(49, 8))
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def test_floordiv(self):
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stmt = lambda y, a, b: y.eq(a // b)
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self.assertStatement(stmt, [C(2, 4), C(1, 4)], C(2, 8))
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self.assertStatement(stmt, [C(2, 4), C(2, 4)], C(1, 8))
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self.assertStatement(stmt, [C(7, 4), C(2, 4)], C(3, 8))
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def test_and(self):
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stmt = lambda y, a, b: y.eq(a & b)
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self.assertStatement(stmt, [C(0b1100, 4), C(0b1010, 4)], C(0b1000, 4))
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def test_or(self):
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stmt = lambda y, a, b: y.eq(a | b)
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self.assertStatement(stmt, [C(0b1100, 4), C(0b1010, 4)], C(0b1110, 4))
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def test_xor_binary(self):
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stmt = lambda y, a, b: y.eq(a ^ b)
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self.assertStatement(stmt, [C(0b1100, 4), C(0b1010, 4)], C(0b0110, 4))
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def test_shl(self):
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stmt = lambda y, a, b: y.eq(a << b)
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self.assertStatement(stmt, [C(0b1001, 4), C(0)], C(0b1001, 5))
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self.assertStatement(stmt, [C(0b1001, 4), C(3)], C(0b1001000, 7))
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def test_shr(self):
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stmt = lambda y, a, b: y.eq(a >> b)
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self.assertStatement(stmt, [C(0b1001, 4), C(0)], C(0b1001, 4))
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self.assertStatement(stmt, [C(0b1001, 4), C(2)], C(0b10, 4))
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def test_eq(self):
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stmt = lambda y, a, b: y.eq(a == b)
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self.assertStatement(stmt, [C(0, 4), C(0, 4)], C(1))
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self.assertStatement(stmt, [C(0, 4), C(1, 4)], C(0))
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self.assertStatement(stmt, [C(1, 4), C(0, 4)], C(0))
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def test_ne(self):
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stmt = lambda y, a, b: y.eq(a != b)
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self.assertStatement(stmt, [C(0, 4), C(0, 4)], C(0))
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self.assertStatement(stmt, [C(0, 4), C(1, 4)], C(1))
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self.assertStatement(stmt, [C(1, 4), C(0, 4)], C(1))
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def test_lt(self):
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stmt = lambda y, a, b: y.eq(a < b)
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self.assertStatement(stmt, [C(0, 4), C(0, 4)], C(0))
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self.assertStatement(stmt, [C(0, 4), C(1, 4)], C(1))
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self.assertStatement(stmt, [C(1, 4), C(0, 4)], C(0))
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def test_ge(self):
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stmt = lambda y, a, b: y.eq(a >= b)
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self.assertStatement(stmt, [C(0, 4), C(0, 4)], C(1))
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self.assertStatement(stmt, [C(0, 4), C(1, 4)], C(0))
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self.assertStatement(stmt, [C(1, 4), C(0, 4)], C(1))
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def test_gt(self):
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stmt = lambda y, a, b: y.eq(a > b)
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self.assertStatement(stmt, [C(0, 4), C(0, 4)], C(0))
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self.assertStatement(stmt, [C(0, 4), C(1, 4)], C(0))
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self.assertStatement(stmt, [C(1, 4), C(0, 4)], C(1))
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def test_le(self):
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stmt = lambda y, a, b: y.eq(a <= b)
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self.assertStatement(stmt, [C(0, 4), C(0, 4)], C(1))
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self.assertStatement(stmt, [C(0, 4), C(1, 4)], C(1))
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self.assertStatement(stmt, [C(1, 4), C(0, 4)], C(0))
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def test_mux(self):
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stmt = lambda y, a, b, c: y.eq(Mux(c, a, b))
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self.assertStatement(stmt, [C(2, 4), C(3, 4), C(0)], C(3, 4))
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self.assertStatement(stmt, [C(2, 4), C(3, 4), C(1)], C(2, 4))
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def test_slice(self):
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stmt1 = lambda y, a: y.eq(a[2])
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self.assertStatement(stmt1, [C(0b10110100, 8)], C(0b1, 1))
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stmt2 = lambda y, a: y.eq(a[2:4])
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self.assertStatement(stmt2, [C(0b10110100, 8)], C(0b01, 2))
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def test_slice_lhs(self):
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stmt1 = lambda y, a: y[2].eq(a)
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self.assertStatement(stmt1, [C(0b0, 1)], C(0b11111011, 8), reset=0b11111111)
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stmt2 = lambda y, a: y[2:4].eq(a)
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self.assertStatement(stmt2, [C(0b01, 2)], C(0b11110111, 8), reset=0b11111011)
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def test_bit_select(self):
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stmt = lambda y, a, b: y.eq(a.bit_select(b, 3))
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self.assertStatement(stmt, [C(0b10110100, 8), C(0)], C(0b100, 3))
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self.assertStatement(stmt, [C(0b10110100, 8), C(2)], C(0b101, 3))
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self.assertStatement(stmt, [C(0b10110100, 8), C(3)], C(0b110, 3))
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def test_bit_select_lhs(self):
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stmt = lambda y, a, b: y.bit_select(a, 3).eq(b)
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self.assertStatement(stmt, [C(0), C(0b100, 3)], C(0b11111100, 8), reset=0b11111111)
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self.assertStatement(stmt, [C(2), C(0b101, 3)], C(0b11110111, 8), reset=0b11111111)
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self.assertStatement(stmt, [C(3), C(0b110, 3)], C(0b11110111, 8), reset=0b11111111)
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def test_word_select(self):
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stmt = lambda y, a, b: y.eq(a.word_select(b, 3))
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self.assertStatement(stmt, [C(0b10110100, 8), C(0)], C(0b100, 3))
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self.assertStatement(stmt, [C(0b10110100, 8), C(1)], C(0b110, 3))
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self.assertStatement(stmt, [C(0b10110100, 8), C(2)], C(0b010, 3))
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def test_word_select_lhs(self):
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stmt = lambda y, a, b: y.word_select(a, 3).eq(b)
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self.assertStatement(stmt, [C(0), C(0b100, 3)], C(0b11111100, 8), reset=0b11111111)
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self.assertStatement(stmt, [C(1), C(0b101, 3)], C(0b11101111, 8), reset=0b11111111)
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self.assertStatement(stmt, [C(2), C(0b110, 3)], C(0b10111111, 8), reset=0b11111111)
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def test_cat(self):
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stmt = lambda y, *xs: y.eq(Cat(*xs))
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self.assertStatement(stmt, [C(0b10, 2), C(0b01, 2)], C(0b0110, 4))
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def test_cat_lhs(self):
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l = Signal(3)
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m = Signal(3)
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n = Signal(3)
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stmt = lambda y, a: [Cat(l, m, n).eq(a), y.eq(Cat(n, m, l))]
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self.assertStatement(stmt, [C(0b100101110, 9)], C(0b110101100, 9))
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def test_nested_cat_lhs(self):
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l = Signal(3)
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m = Signal(3)
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n = Signal(3)
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stmt = lambda y, a: [Cat(Cat(l, Cat(m)), n).eq(a), y.eq(Cat(n, m, l))]
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self.assertStatement(stmt, [C(0b100101110, 9)], C(0b110101100, 9))
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def test_record(self):
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rec = Record([
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("l", 1),
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("m", 2),
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])
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stmt = lambda y, a: [rec.eq(a), y.eq(rec)]
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self.assertStatement(stmt, [C(0b101, 3)], C(0b101, 3))
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def test_repl(self):
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stmt = lambda y, a: y.eq(Repl(a, 3))
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self.assertStatement(stmt, [C(0b10, 2)], C(0b101010, 6))
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def test_array(self):
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array = Array([1, 4, 10])
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stmt = lambda y, a: y.eq(array[a])
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self.assertStatement(stmt, [C(0)], C(1))
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self.assertStatement(stmt, [C(1)], C(4))
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self.assertStatement(stmt, [C(2)], C(10))
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def test_array_oob(self):
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array = Array([1, 4, 10])
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stmt = lambda y, a: y.eq(array[a])
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self.assertStatement(stmt, [C(3)], C(10))
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self.assertStatement(stmt, [C(4)], C(10))
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def test_array_lhs(self):
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l = Signal(3, reset=1)
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m = Signal(3, reset=4)
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n = Signal(3, reset=7)
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array = Array([l, m, n])
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stmt = lambda y, a, b: [array[a].eq(b), y.eq(Cat(*array))]
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self.assertStatement(stmt, [C(0), C(0b000)], C(0b111100000))
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self.assertStatement(stmt, [C(1), C(0b010)], C(0b111010001))
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self.assertStatement(stmt, [C(2), C(0b100)], C(0b100100001))
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def test_array_lhs_oob(self):
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l = Signal(3)
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m = Signal(3)
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n = Signal(3)
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array = Array([l, m, n])
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stmt = lambda y, a, b: [array[a].eq(b), y.eq(Cat(*array))]
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self.assertStatement(stmt, [C(3), C(0b001)], C(0b001000000))
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self.assertStatement(stmt, [C(4), C(0b010)], C(0b010000000))
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def test_array_index(self):
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array = Array(Array(x * y for y in range(10)) for x in range(10))
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stmt = lambda y, a, b: y.eq(array[a][b])
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for x in range(10):
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for y in range(10):
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self.assertStatement(stmt, [C(x), C(y)], C(x * y))
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def test_array_attr(self):
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from collections import namedtuple
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pair = namedtuple("pair", ("p", "n"))
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array = Array(pair(x, -x) for x in range(10))
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stmt = lambda y, a: y.eq(array[a].p + array[a].n)
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for i in range(10):
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self.assertStatement(stmt, [C(i)], C(0))
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class SimulatorIntegrationTestCase(FHDLTestCase):
|
||
|
|
@contextmanager
|
||
|
|
def assertSimulation(self, module, deadline=None):
|
||
|
|
sim = Simulator(module)
|
||
|
|
yield sim
|
||
|
|
with sim.write_vcd("test.vcd", "test.gtkw"):
|
||
|
|
if deadline is None:
|
||
|
|
sim.run()
|
||
|
|
else:
|
||
|
|
sim.run_until(deadline)
|
||
|
|
|
||
|
|
def setUp_counter(self):
|
||
|
|
self.count = Signal(3, reset=4)
|
||
|
|
self.sync = ClockDomain()
|
||
|
|
|
||
|
|
self.m = Module()
|
||
|
|
self.m.d.sync += self.count.eq(self.count + 1)
|
||
|
|
self.m.domains += self.sync
|
||
|
|
|
||
|
|
def test_counter_process(self):
|
||
|
|
self.setUp_counter()
|
||
|
|
with self.assertSimulation(self.m) as sim:
|
||
|
|
def process():
|
||
|
|
self.assertEqual((yield self.count), 4)
|
||
|
|
yield Delay(1e-6)
|
||
|
|
self.assertEqual((yield self.count), 4)
|
||
|
|
yield self.sync.clk.eq(1)
|
||
|
|
self.assertEqual((yield self.count), 4)
|
||
|
|
yield Settle()
|
||
|
|
self.assertEqual((yield self.count), 5)
|
||
|
|
yield Delay(1e-6)
|
||
|
|
self.assertEqual((yield self.count), 5)
|
||
|
|
yield self.sync.clk.eq(0)
|
||
|
|
self.assertEqual((yield self.count), 5)
|
||
|
|
yield Settle()
|
||
|
|
self.assertEqual((yield self.count), 5)
|
||
|
|
for _ in range(3):
|
||
|
|
yield Delay(1e-6)
|
||
|
|
yield self.sync.clk.eq(1)
|
||
|
|
yield Delay(1e-6)
|
||
|
|
yield self.sync.clk.eq(0)
|
||
|
|
self.assertEqual((yield self.count), 0)
|
||
|
|
sim.add_process(process)
|
||
|
|
|
||
|
|
def test_counter_clock_and_sync_process(self):
|
||
|
|
self.setUp_counter()
|
||
|
|
with self.assertSimulation(self.m) as sim:
|
||
|
|
sim.add_clock(1e-6, domain="sync")
|
||
|
|
def process():
|
||
|
|
self.assertEqual((yield self.count), 4)
|
||
|
|
self.assertEqual((yield self.sync.clk), 1)
|
||
|
|
yield
|
||
|
|
self.assertEqual((yield self.count), 5)
|
||
|
|
self.assertEqual((yield self.sync.clk), 1)
|
||
|
|
for _ in range(3):
|
||
|
|
yield
|
||
|
|
self.assertEqual((yield self.count), 0)
|
||
|
|
sim.add_sync_process(process)
|
||
|
|
|
||
|
|
def test_reset(self):
|
||
|
|
self.setUp_counter()
|
||
|
|
sim = Simulator(self.m)
|
||
|
|
sim.add_clock(1e-6)
|
||
|
|
times = 0
|
||
|
|
def process():
|
||
|
|
nonlocal times
|
||
|
|
self.assertEqual((yield self.count), 4)
|
||
|
|
yield
|
||
|
|
self.assertEqual((yield self.count), 5)
|
||
|
|
yield
|
||
|
|
self.assertEqual((yield self.count), 6)
|
||
|
|
yield
|
||
|
|
times += 1
|
||
|
|
sim.add_sync_process(process)
|
||
|
|
sim.run()
|
||
|
|
sim.reset()
|
||
|
|
sim.run()
|
||
|
|
self.assertEqual(times, 2)
|
||
|
|
|
||
|
|
def setUp_alu(self):
|
||
|
|
self.a = Signal(8)
|
||
|
|
self.b = Signal(8)
|
||
|
|
self.o = Signal(8)
|
||
|
|
self.x = Signal(8)
|
||
|
|
self.s = Signal(2)
|
||
|
|
self.sync = ClockDomain(reset_less=True)
|
||
|
|
|
||
|
|
self.m = Module()
|
||
|
|
self.m.d.comb += self.x.eq(self.a ^ self.b)
|
||
|
|
with self.m.Switch(self.s):
|
||
|
|
with self.m.Case(0):
|
||
|
|
self.m.d.sync += self.o.eq(self.a + self.b)
|
||
|
|
with self.m.Case(1):
|
||
|
|
self.m.d.sync += self.o.eq(self.a - self.b)
|
||
|
|
with self.m.Case():
|
||
|
|
self.m.d.sync += self.o.eq(0)
|
||
|
|
self.m.domains += self.sync
|
||
|
|
|
||
|
|
def test_alu(self):
|
||
|
|
self.setUp_alu()
|
||
|
|
with self.assertSimulation(self.m) as sim:
|
||
|
|
sim.add_clock(1e-6)
|
||
|
|
def process():
|
||
|
|
yield self.a.eq(5)
|
||
|
|
yield self.b.eq(1)
|
||
|
|
yield
|
||
|
|
self.assertEqual((yield self.x), 4)
|
||
|
|
yield
|
||
|
|
self.assertEqual((yield self.o), 6)
|
||
|
|
yield self.s.eq(1)
|
||
|
|
yield
|
||
|
|
yield
|
||
|
|
self.assertEqual((yield self.o), 4)
|
||
|
|
yield self.s.eq(2)
|
||
|
|
yield
|
||
|
|
yield
|
||
|
|
self.assertEqual((yield self.o), 0)
|
||
|
|
sim.add_sync_process(process)
|
||
|
|
|
||
|
|
def setUp_multiclock(self):
|
||
|
|
self.sys = ClockDomain()
|
||
|
|
self.pix = ClockDomain()
|
||
|
|
|
||
|
|
self.m = Module()
|
||
|
|
self.m.domains += self.sys, self.pix
|
||
|
|
|
||
|
|
def test_multiclock(self):
|
||
|
|
self.setUp_multiclock()
|
||
|
|
with self.assertSimulation(self.m) as sim:
|
||
|
|
sim.add_clock(1e-6, domain="sys")
|
||
|
|
sim.add_clock(0.3e-6, domain="pix")
|
||
|
|
|
||
|
|
def sys_process():
|
||
|
|
yield Passive()
|
||
|
|
yield
|
||
|
|
yield
|
||
|
|
self.fail()
|
||
|
|
def pix_process():
|
||
|
|
yield
|
||
|
|
yield
|
||
|
|
yield
|
||
|
|
sim.add_sync_process(sys_process, domain="sys")
|
||
|
|
sim.add_sync_process(pix_process, domain="pix")
|
||
|
|
|
||
|
|
def setUp_lhs_rhs(self):
|
||
|
|
self.i = Signal(8)
|
||
|
|
self.o = Signal(8)
|
||
|
|
|
||
|
|
self.m = Module()
|
||
|
|
self.m.d.comb += self.o.eq(self.i)
|
||
|
|
|
||
|
|
def test_complex_lhs_rhs(self):
|
||
|
|
self.setUp_lhs_rhs()
|
||
|
|
with self.assertSimulation(self.m) as sim:
|
||
|
|
def process():
|
||
|
|
yield self.i.eq(0b10101010)
|
||
|
|
yield self.i[:4].eq(-1)
|
||
|
|
yield Settle()
|
||
|
|
self.assertEqual((yield self.i[:4]), 0b1111)
|
||
|
|
self.assertEqual((yield self.i), 0b10101111)
|
||
|
|
sim.add_process(process)
|
||
|
|
|
||
|
|
def test_run_until(self):
|
||
|
|
m = Module()
|
||
|
|
s = Signal()
|
||
|
|
m.d.sync += s.eq(0)
|
||
|
|
with self.assertSimulation(m, deadline=100e-6) as sim:
|
||
|
|
sim.add_clock(1e-6)
|
||
|
|
def process():
|
||
|
|
for _ in range(101):
|
||
|
|
yield Delay(1e-6)
|
||
|
|
self.fail()
|
||
|
|
sim.add_process(process)
|
||
|
|
|
||
|
|
def test_add_process_wrong(self):
|
||
|
|
with self.assertSimulation(Module()) as sim:
|
||
|
|
with self.assertRaises(TypeError,
|
||
|
|
msg="Cannot add a process 1 because it is not a generator function"):
|
||
|
|
sim.add_process(1)
|
||
|
|
|
||
|
|
def test_add_process_wrong_generator(self):
|
||
|
|
with self.assertSimulation(Module()) as sim:
|
||
|
|
with self.assertWarns(DeprecationWarning,
|
||
|
|
msg="instead of generators, use generator functions as processes; "
|
||
|
|
"this allows the simulator to be repeatedly reset"):
|
||
|
|
def process():
|
||
|
|
yield Delay()
|
||
|
|
sim.add_process(process())
|
||
|
|
|
||
|
|
def test_add_clock_wrong_twice(self):
|
||
|
|
m = Module()
|
||
|
|
s = Signal()
|
||
|
|
m.d.sync += s.eq(0)
|
||
|
|
with self.assertSimulation(m) as sim:
|
||
|
|
sim.add_clock(1)
|
||
|
|
with self.assertRaises(ValueError,
|
||
|
|
msg="Domain 'sync' already has a clock driving it"):
|
||
|
|
sim.add_clock(1)
|
||
|
|
|
||
|
|
def test_add_clock_wrong_missing(self):
|
||
|
|
m = Module()
|
||
|
|
with self.assertSimulation(m) as sim:
|
||
|
|
with self.assertRaises(ValueError,
|
||
|
|
msg="Domain 'sync' is not present in simulation"):
|
||
|
|
sim.add_clock(1)
|
||
|
|
|
||
|
|
def test_add_clock_if_exists(self):
|
||
|
|
m = Module()
|
||
|
|
with self.assertSimulation(m) as sim:
|
||
|
|
sim.add_clock(1, if_exists=True)
|
||
|
|
|
||
|
|
def test_command_wrong(self):
|
||
|
|
survived = False
|
||
|
|
with self.assertSimulation(Module()) as sim:
|
||
|
|
def process():
|
||
|
|
nonlocal survived
|
||
|
|
with self.assertRaisesRegex(TypeError,
|
||
|
|
regex=r"Received unsupported command 1 from process .+?"):
|
||
|
|
yield 1
|
||
|
|
yield Settle()
|
||
|
|
survived = True
|
||
|
|
sim.add_process(process)
|
||
|
|
self.assertTrue(survived)
|
||
|
|
|
||
|
|
def setUp_memory(self, rd_synchronous=True, rd_transparent=True, wr_granularity=None):
|
||
|
|
self.m = Module()
|
||
|
|
self.memory = Memory(width=8, depth=4, init=[0xaa, 0x55])
|
||
|
|
self.m.submodules.rdport = self.rdport = \
|
||
|
|
self.memory.read_port(domain="sync" if rd_synchronous else "comb",
|
||
|
|
transparent=rd_transparent)
|
||
|
|
self.m.submodules.wrport = self.wrport = \
|
||
|
|
self.memory.write_port(granularity=wr_granularity)
|
||
|
|
|
||
|
|
def test_memory_init(self):
|
||
|
|
self.setUp_memory()
|
||
|
|
with self.assertSimulation(self.m) as sim:
|
||
|
|
def process():
|
||
|
|
self.assertEqual((yield self.rdport.data), 0xaa)
|
||
|
|
yield self.rdport.addr.eq(1)
|
||
|
|
yield
|
||
|
|
yield
|
||
|
|
self.assertEqual((yield self.rdport.data), 0x55)
|
||
|
|
yield self.rdport.addr.eq(2)
|
||
|
|
yield
|
||
|
|
yield
|
||
|
|
self.assertEqual((yield self.rdport.data), 0x00)
|
||
|
|
sim.add_clock(1e-6)
|
||
|
|
sim.add_sync_process(process)
|
||
|
|
|
||
|
|
def test_memory_write(self):
|
||
|
|
self.setUp_memory()
|
||
|
|
with self.assertSimulation(self.m) as sim:
|
||
|
|
def process():
|
||
|
|
yield self.wrport.addr.eq(4)
|
||
|
|
yield self.wrport.data.eq(0x33)
|
||
|
|
yield self.wrport.en.eq(1)
|
||
|
|
yield
|
||
|
|
yield self.wrport.en.eq(0)
|
||
|
|
yield self.rdport.addr.eq(4)
|
||
|
|
yield
|
||
|
|
self.assertEqual((yield self.rdport.data), 0x33)
|
||
|
|
sim.add_clock(1e-6)
|
||
|
|
sim.add_sync_process(process)
|
||
|
|
|
||
|
|
def test_memory_write_granularity(self):
|
||
|
|
self.setUp_memory(wr_granularity=4)
|
||
|
|
with self.assertSimulation(self.m) as sim:
|
||
|
|
def process():
|
||
|
|
yield self.wrport.data.eq(0x50)
|
||
|
|
yield self.wrport.en.eq(0b00)
|
||
|
|
yield
|
||
|
|
yield self.wrport.en.eq(0)
|
||
|
|
yield
|
||
|
|
self.assertEqual((yield self.rdport.data), 0xaa)
|
||
|
|
yield self.wrport.en.eq(0b10)
|
||
|
|
yield
|
||
|
|
yield self.wrport.en.eq(0)
|
||
|
|
yield
|
||
|
|
self.assertEqual((yield self.rdport.data), 0x5a)
|
||
|
|
yield self.wrport.data.eq(0x33)
|
||
|
|
yield self.wrport.en.eq(0b01)
|
||
|
|
yield
|
||
|
|
yield self.wrport.en.eq(0)
|
||
|
|
yield
|
||
|
|
self.assertEqual((yield self.rdport.data), 0x53)
|
||
|
|
sim.add_clock(1e-6)
|
||
|
|
sim.add_sync_process(process)
|
||
|
|
|
||
|
|
def test_memory_read_before_write(self):
|
||
|
|
self.setUp_memory(rd_transparent=False)
|
||
|
|
with self.assertSimulation(self.m) as sim:
|
||
|
|
def process():
|
||
|
|
yield self.wrport.data.eq(0x33)
|
||
|
|
yield self.wrport.en.eq(1)
|
||
|
|
yield
|
||
|
|
self.assertEqual((yield self.rdport.data), 0xaa)
|
||
|
|
yield
|
||
|
|
self.assertEqual((yield self.rdport.data), 0xaa)
|
||
|
|
yield Settle()
|
||
|
|
self.assertEqual((yield self.rdport.data), 0x33)
|
||
|
|
sim.add_clock(1e-6)
|
||
|
|
sim.add_sync_process(process)
|
||
|
|
|
||
|
|
def test_memory_write_through(self):
|
||
|
|
self.setUp_memory(rd_transparent=True)
|
||
|
|
with self.assertSimulation(self.m) as sim:
|
||
|
|
def process():
|
||
|
|
yield self.wrport.data.eq(0x33)
|
||
|
|
yield self.wrport.en.eq(1)
|
||
|
|
yield
|
||
|
|
self.assertEqual((yield self.rdport.data), 0xaa)
|
||
|
|
yield Settle()
|
||
|
|
self.assertEqual((yield self.rdport.data), 0x33)
|
||
|
|
yield
|
||
|
|
yield self.rdport.addr.eq(1)
|
||
|
|
yield Settle()
|
||
|
|
self.assertEqual((yield self.rdport.data), 0x33)
|
||
|
|
sim.add_clock(1e-6)
|
||
|
|
sim.add_sync_process(process)
|
||
|
|
|
||
|
|
def test_memory_async_read_write(self):
|
||
|
|
self.setUp_memory(rd_synchronous=False)
|
||
|
|
with self.assertSimulation(self.m) as sim:
|
||
|
|
def process():
|
||
|
|
yield self.rdport.addr.eq(0)
|
||
|
|
yield Settle()
|
||
|
|
self.assertEqual((yield self.rdport.data), 0xaa)
|
||
|
|
yield self.rdport.addr.eq(1)
|
||
|
|
yield Settle()
|
||
|
|
self.assertEqual((yield self.rdport.data), 0x55)
|
||
|
|
yield self.rdport.addr.eq(0)
|
||
|
|
yield self.wrport.addr.eq(0)
|
||
|
|
yield self.wrport.data.eq(0x33)
|
||
|
|
yield self.wrport.en.eq(1)
|
||
|
|
yield Tick("sync")
|
||
|
|
self.assertEqual((yield self.rdport.data), 0xaa)
|
||
|
|
yield Settle()
|
||
|
|
self.assertEqual((yield self.rdport.data), 0x33)
|
||
|
|
sim.add_clock(1e-6)
|
||
|
|
sim.add_process(process)
|
||
|
|
|
||
|
|
def test_memory_read_only(self):
|
||
|
|
self.m = Module()
|
||
|
|
self.memory = Memory(width=8, depth=4, init=[0xaa, 0x55])
|
||
|
|
self.m.submodules.rdport = self.rdport = self.memory.read_port()
|
||
|
|
with self.assertSimulation(self.m) as sim:
|
||
|
|
def process():
|
||
|
|
self.assertEqual((yield self.rdport.data), 0xaa)
|
||
|
|
yield self.rdport.addr.eq(1)
|
||
|
|
yield
|
||
|
|
yield
|
||
|
|
self.assertEqual((yield self.rdport.data), 0x55)
|
||
|
|
sim.add_clock(1e-6)
|
||
|
|
sim.add_sync_process(process)
|
||
|
|
|
||
|
|
def test_sample_helpers(self):
|
||
|
|
m = Module()
|
||
|
|
s = Signal(2)
|
||
|
|
def mk(x):
|
||
|
|
y = Signal.like(x)
|
||
|
|
m.d.comb += y.eq(x)
|
||
|
|
return y
|
||
|
|
p0, r0, f0, s0 = mk(Past(s, 0)), mk(Rose(s)), mk(Fell(s)), mk(Stable(s))
|
||
|
|
p1, r1, f1, s1 = mk(Past(s)), mk(Rose(s, 1)), mk(Fell(s, 1)), mk(Stable(s, 1))
|
||
|
|
p2, r2, f2, s2 = mk(Past(s, 2)), mk(Rose(s, 2)), mk(Fell(s, 2)), mk(Stable(s, 2))
|
||
|
|
p3, r3, f3, s3 = mk(Past(s, 3)), mk(Rose(s, 3)), mk(Fell(s, 3)), mk(Stable(s, 3))
|
||
|
|
with self.assertSimulation(m) as sim:
|
||
|
|
def process_gen():
|
||
|
|
yield s.eq(0b10)
|
||
|
|
yield
|
||
|
|
yield
|
||
|
|
yield s.eq(0b01)
|
||
|
|
yield
|
||
|
|
def process_check():
|
||
|
|
yield
|
||
|
|
yield
|
||
|
|
yield
|
||
|
|
|
||
|
|
self.assertEqual((yield p0), 0b01)
|
||
|
|
self.assertEqual((yield p1), 0b10)
|
||
|
|
self.assertEqual((yield p2), 0b10)
|
||
|
|
self.assertEqual((yield p3), 0b00)
|
||
|
|
|
||
|
|
self.assertEqual((yield s0), 0b0)
|
||
|
|
self.assertEqual((yield s1), 0b1)
|
||
|
|
self.assertEqual((yield s2), 0b0)
|
||
|
|
self.assertEqual((yield s3), 0b1)
|
||
|
|
|
||
|
|
self.assertEqual((yield r0), 0b01)
|
||
|
|
self.assertEqual((yield r1), 0b00)
|
||
|
|
self.assertEqual((yield r2), 0b10)
|
||
|
|
self.assertEqual((yield r3), 0b00)
|
||
|
|
|
||
|
|
self.assertEqual((yield f0), 0b10)
|
||
|
|
self.assertEqual((yield f1), 0b00)
|
||
|
|
self.assertEqual((yield f2), 0b00)
|
||
|
|
self.assertEqual((yield f3), 0b00)
|
||
|
|
sim.add_clock(1e-6)
|
||
|
|
sim.add_sync_process(process_gen)
|
||
|
|
sim.add_sync_process(process_check)
|
||
|
|
|
||
|
|
def test_vcd_wrong_nonzero_time(self):
|
||
|
|
s = Signal()
|
||
|
|
m = Module()
|
||
|
|
m.d.sync += s.eq(s)
|
||
|
|
sim = Simulator(m)
|
||
|
|
sim.add_clock(1e-6)
|
||
|
|
sim.run_until(1e-5)
|
||
|
|
with self.assertRaisesRegex(ValueError,
|
||
|
|
regex=r"^Cannot start writing waveforms after advancing simulation time$"):
|
||
|
|
with sim.write_vcd(open(os.path.devnull, "wt")):
|
||
|
|
pass
|
||
|
|
|
||
|
|
def test_vcd_wrong_twice(self):
|
||
|
|
s = Signal()
|
||
|
|
m = Module()
|
||
|
|
m.d.sync += s.eq(s)
|
||
|
|
sim = Simulator(m)
|
||
|
|
sim.add_clock(1e-6)
|
||
|
|
with self.assertRaisesRegex(ValueError,
|
||
|
|
regex=r"^Already writing waveforms to .+$"):
|
||
|
|
with sim.write_vcd(open(os.path.devnull, "wt")):
|
||
|
|
with sim.write_vcd(open(os.path.devnull, "wt")):
|
||
|
|
pass
|
||
|
|
|
||
|
|
|
||
|
|
class SimulatorRegressionTestCase(FHDLTestCase):
|
||
|
|
def test_bug_325(self):
|
||
|
|
dut = Module()
|
||
|
|
dut.d.comb += Signal().eq(Cat())
|
||
|
|
Simulator(dut).run()
|
||
|
|
|
||
|
|
def test_bug_325_bis(self):
|
||
|
|
dut = Module()
|
||
|
|
dut.d.comb += Signal().eq(Repl(Const(1), 0))
|
||
|
|
Simulator(dut).run()
|