75 lines
2.8 KiB
Python
75 lines
2.8 KiB
Python
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import argparse
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from .hdl.ir import Fragment
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from .back import rtlil, verilog, pysim
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__all__ = ["main"]
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def main_parser(parser=None):
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if parser is None:
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parser = argparse.ArgumentParser()
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p_action = parser.add_subparsers(dest="action")
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p_generate = p_action.add_parser("generate",
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help="generate RTLIL or Verilog from the design")
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p_generate.add_argument("-t", "--type", dest="generate_type",
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metavar="LANGUAGE", choices=["il", "v"],
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default="v",
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help="generate LANGUAGE (il for RTLIL, v for Verilog; default: %(default)s)")
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p_generate.add_argument("generate_file",
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metavar="FILE", type=argparse.FileType("w"), nargs="?",
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help="write generated code to FILE")
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p_simulate = p_action.add_parser(
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"simulate", help="simulate the design")
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p_simulate.add_argument("-v", "--vcd-file",
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metavar="VCD-FILE", type=argparse.FileType("w"),
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help="write execution trace to VCD-FILE")
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p_simulate.add_argument("-w", "--gtkw-file",
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metavar="GTKW-FILE", type=argparse.FileType("w"),
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help="write GTKWave configuration to GTKW-FILE")
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p_simulate.add_argument("-p", "--period", dest="sync_period",
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metavar="TIME", type=float, default=1e-6,
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help="set 'sync' clock domain period to TIME (default: %(default)s)")
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p_simulate.add_argument("-c", "--clocks", dest="sync_clocks",
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metavar="COUNT", type=int, required=True,
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help="simulate for COUNT 'sync' clock periods")
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return parser
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def main_runner(parser, args, design, platform=None, name="top", ports=()):
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if args.action == "generate":
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fragment = Fragment.get(design, platform)
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generate_type = args.generate_type
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if generate_type is None and args.generate_file:
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if args.generate_file.name.endswith(".v"):
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generate_type = "v"
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if args.generate_file.name.endswith(".il"):
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generate_type = "il"
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if generate_type is None:
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parser.error("specify file type explicitly with -t")
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if generate_type == "il":
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output = rtlil.convert(fragment, name=name, ports=ports)
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if generate_type == "v":
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output = verilog.convert(fragment, name=name, ports=ports)
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if args.generate_file:
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args.generate_file.write(output)
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else:
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print(output)
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if args.action == "simulate":
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fragment = Fragment.get(design, platform)
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sim = pysim.Simulator(fragment)
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sim.add_clock(args.sync_period)
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with sim.write_vcd(vcd_file=args.vcd_file, gtkw_file=args.gtkw_file, traces=ports):
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sim.run_until(args.sync_period * args.sync_clocks, run_passive=True)
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def main(*args, **kwargs):
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parser = main_parser()
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main_runner(parser, parser.parse_args(), *args, **kwargs)
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