riscv-formal-nmigen/insns/insn_lui.py

from insn_U_type import *

class rvfi_insn_lui(rvfi_insn_U_type):
    def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
        super(rvfi_insn_lui, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN)
    def ports(self):
        return super(rvfi_insn_lui, self).ports()
    def elaborate(self, platform):
        m = super(rvfi_insn_lui, self).elaborate(platform)

        # LUI instruction
        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_opcode == 0b0110111))
        m.d.comb += self.spec_rd_addr.eq(self.insn_rd)
        m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.insn_imm, 0))
        m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)

        # default assignments
        m.d.comb += self.spec_rs1_addr.eq(0)
        m.d.comb += self.spec_rs2_addr.eq(0)
        m.d.comb += self.spec_trap.eq(~self.misa_ok)
        m.d.comb += self.spec_mem_addr.eq(0)
        m.d.comb += self.spec_mem_rmask.eq(0)
        m.d.comb += self.spec_mem_wmask.eq(0)
        m.d.comb += self.spec_mem_wdata.eq(0)

        return m