232 lines
9.6 KiB
Python
232 lines
9.6 KiB
Python
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from .insn_lui import *
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from .insn_auipc import *
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from .insn_jal import *
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from .insn_jalr import *
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from .insn_beq import *
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from .insn_bne import *
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from .insn_blt import *
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from .insn_bge import *
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from .insn_bltu import *
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from .insn_bgeu import *
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from .insn_lb import *
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from .insn_lh import *
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from .insn_lw import *
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from .insn_lbu import *
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from .insn_lhu import *
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from .insn_sb import *
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from .insn_sh import *
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from .insn_sw import *
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from .insn_addi import *
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from .insn_slti import *
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from .insn_sltiu import *
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from .insn_xori import *
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from .insn_ori import *
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from .insn_andi import *
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from .insn_slli import *
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from .insn_srli import *
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from .insn_srai import *
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from .insn_add import *
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from .insn_sub import *
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from .insn_sll import *
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from .insn_slt import *
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from .insn_sltu import *
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from .insn_xor import *
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from .insn_srl import *
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from .insn_sra import *
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from .insn_or import *
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from .insn_and import *
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from .insn_mul import *
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from .insn_mulh import *
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from .insn_mulhsu import *
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from .insn_mulhu import *
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from .insn_div import *
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from .insn_divu import *
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from .insn_rem import *
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from .insn_remu import *
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"""
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RV32M Standard Extension
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"""
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class IsaRV32M(Elaboratable):
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def __init__(self, params):
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# Core-specific parameters
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self.params = params
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# Input ports
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self.rvfi_valid = Signal(1)
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self.rvfi_insn = Signal(self.params.ilen)
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self.rvfi_pc_rdata = Signal(self.params.xlen)
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self.rvfi_rs1_rdata = Signal(self.params.xlen)
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self.rvfi_rs2_rdata = Signal(self.params.xlen)
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self.rvfi_mem_rdata = Signal(self.params.xlen)
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if self.params.csr_misa:
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self.rvfi_csr_misa_rdata = Signal(self.params.xlen)
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# Output ports
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if self.params.csr_misa:
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self.spec_csr_misa_rmask = Signal(self.params.xlen)
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self.spec_valid = Signal(1)
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self.spec_trap = Signal(1)
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self.spec_rs1_addr = Signal(5)
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self.spec_rs2_addr = Signal(5)
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self.spec_rd_addr = Signal(5)
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self.spec_rd_wdata = Signal(self.params.xlen)
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self.spec_pc_wdata = Signal(self.params.xlen)
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self.spec_mem_addr = Signal(self.params.xlen)
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self.spec_mem_rmask = Signal(int(self.params.xlen // 8))
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self.spec_mem_wmask = Signal(int(self.params.xlen // 8))
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self.spec_mem_wdata = Signal(self.params.xlen)
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def ports(self):
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input_ports = [
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self.rvfi_valid,
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self.rvfi_insn,
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self.rvfi_pc_rdata,
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self.rvfi_rs1_rdata,
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self.rvfi_rs2_rdata,
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self.rvfi_mem_rdata
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]
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if self.params.csr_misa:
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input_ports.append(self.rvfi_csr_misa_rdata)
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output_ports = [
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self.spec_valid,
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self.spec_trap,
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self.spec_rs1_addr,
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self.spec_rs2_addr,
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self.spec_rd_addr,
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self.spec_rd_wdata,
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self.spec_pc_wdata,
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self.spec_mem_addr,
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self.spec_mem_rmask,
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self.spec_mem_wmask,
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self.spec_mem_wdata
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]
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if self.params.csr_misa:
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output_ports.append(self.spec_csr_misa_rmask)
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return input_ports + output_ports
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def elaborate(self, platform):
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m = Module()
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insn_submodules = {}
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m.submodules._lui = insn_submodules['lui'] = InsnLui(self.params)
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m.submodules._auipc = insn_submodules['auipc'] = InsnAuipc(self.params)
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m.submodules._jal = insn_submodules['jal'] = InsnJal(self.params)
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m.submodules._jalr = insn_submodules['jalr'] = InsnJalr(self.params)
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m.submodules._beq = insn_submodules['beq'] = InsnBeq(self.params)
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m.submodules._bne = insn_submodules['bne'] = InsnBne(self.params)
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m.submodules._blt = insn_submodules['blt'] = InsnBlt(self.params)
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m.submodules._bge = insn_submodules['bge'] = InsnBge(self.params)
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m.submodules._bltu = insn_submodules['bltu'] = InsnBltu(self.params)
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m.submodules._bgeu = insn_submodules['bgeu'] = InsnBgeu(self.params)
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m.submodules._lb = insn_submodules['lb'] = InsnLb(self.params)
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m.submodules._lh = insn_submodules['lh'] = InsnLh(self.params)
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m.submodules._lw = insn_submodules['lw'] = InsnLw(self.params)
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m.submodules._lbu = insn_submodules['lbu'] = InsnLbu(self.params)
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m.submodules._lhu = insn_submodules['lhu'] = InsnLhu(self.params)
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m.submodules._sb = insn_submodules['sb'] = InsnSb(self.params)
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m.submodules._sh = insn_submodules['Sh'] = InsnSh(self.params)
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m.submodules._sw = insn_submodules['sw'] = InsnSw(self.params)
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m.submodules._addi = insn_submodules['addi'] = InsnAddi(self.params)
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m.submodules._slti = insn_submodules['slti'] = InsnSlti(self.params)
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m.submodules._sltiu = insn_submodules['sltiu'] = InsnSltiu(self.params)
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m.submodules._xori = insn_submodules['xori'] = InsnXori(self.params)
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m.submodules._ori = insn_submodules['ori'] = InsnOri(self.params)
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m.submodules._andi = insn_submodules['andi'] = InsnAndi(self.params)
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m.submodules._slli = insn_submodules['slli'] = InsnSlli(self.params)
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m.submodules._srli = insn_submodules['srli'] = InsnSrli(self.params)
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m.submodules._srai = insn_submodules['srai'] = InsnSrai(self.params)
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m.submodules._add = insn_submodules['add'] = InsnAdd(self.params)
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m.submodules._sub = insn_submodules['sub'] = InsnSub(self.params)
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m.submodules._sll = insn_submodules['sll'] = InsnSll(self.params)
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m.submodules._slt = insn_submodules['slt'] = InsnSlt(self.params)
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m.submodules._sltu = insn_submodules['sltu'] = InsnSltu(self.params)
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m.submodules._xor = insn_submodules['xor'] = InsnXor(self.params)
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m.submodules._srl = insn_submodules['srl'] = InsnSrl(self.params)
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m.submodules._sra = insn_submodules['sra'] = InsnSra(self.params)
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m.submodules._or = insn_submodules['or'] = InsnOr(self.params)
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m.submodules._and = insn_submodules['and'] = InsnAnd(self.params)
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m.submodules._mul = insn_submodules['mul'] = InsnMul(self.params)
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m.submodules._mulh = insn_submodules['mulh'] = InsnMulh(self.params)
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m.submodules._mulhsu = insn_submodules['mulhsu'] = InsnMulhsu(self.params)
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m.submodules._mulhu = insn_submodules['mulhu'] = InsnMulhu(self.params)
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m.submodules._div = insn_submodules['div'] = InsnDiv(self.params)
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m.submodules._divu = insn_submodules['divu'] = InsnDivu(self.params)
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m.submodules._rem = insn_submodules['rem'] = InsnRem(self.params)
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m.submodules._remu = insn_submodules['remu'] = InsnRemu(self.params)
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for _, insn in insn_submodules.items():
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m.d.comb += insn.rvfi_valid.eq(self.rvfi_valid)
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m.d.comb += insn.rvfi_insn.eq(self.rvfi_insn)
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m.d.comb += insn.rvfi_pc_rdata.eq(self.rvfi_pc_rdata)
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m.d.comb += insn.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata)
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m.d.comb += insn.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata)
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m.d.comb += insn.rvfi_mem_rdata.eq(self.rvfi_mem_rdata)
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if self.params.csr_misa:
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m.d.comb += insn.rvfi_csr_misa_rdata.eq(self.rvfi_csr_misa_rdata)
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spec_valid = 0
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for _, insn in insn_submodules.items():
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spec_valid = Mux(insn.spec_valid, insn.spec_valid, spec_valid)
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m.d.comb += self.spec_valid.eq(spec_valid)
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spec_trap = 0
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for _, insn in insn_submodules.items():
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spec_trap = Mux(insn.spec_valid, insn.spec_trap, spec_trap)
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m.d.comb += self.spec_trap.eq(spec_trap)
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spec_rs1_addr = 0
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for _, insn in insn_submodules.items():
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spec_rs1_addr = Mux(insn.spec_valid, insn.spec_rs1_addr, spec_rs1_addr)
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m.d.comb += self.spec_rs1_addr.eq(spec_rs1_addr)
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spec_rs2_addr = 0
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for _, insn in insn_submodules.items():
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spec_rs2_addr = Mux(insn.spec_valid, insn.spec_rs2_addr, spec_rs2_addr)
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m.d.comb += self.spec_rs2_addr.eq(spec_rs2_addr)
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spec_rd_addr = 0
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for _, insn in insn_submodules.items():
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spec_rd_addr = Mux(insn.spec_valid, insn.spec_rd_addr, spec_rd_addr)
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m.d.comb += self.spec_rd_addr.eq(spec_rd_addr)
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spec_rd_wdata = 0
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for _, insn in insn_submodules.items():
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spec_rd_wdata = Mux(insn.spec_valid, insn.spec_rd_wdata, spec_rd_wdata)
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m.d.comb += self.spec_rd_wdata.eq(spec_rd_wdata)
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spec_pc_wdata = 0
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for _, insn in insn_submodules.items():
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spec_pc_wdata = Mux(insn.spec_valid, insn.spec_pc_wdata, spec_pc_wdata)
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m.d.comb += self.spec_pc_wdata.eq(spec_pc_wdata)
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spec_mem_addr = 0
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for _, insn in insn_submodules.items():
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spec_mem_addr = Mux(insn.spec_valid, insn.spec_mem_addr, spec_mem_addr)
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m.d.comb += self.spec_mem_addr.eq(spec_mem_addr)
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spec_mem_rmask = 0
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for _, insn in insn_submodules.items():
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spec_mem_rmask = Mux(insn.spec_valid, insn.spec_mem_rmask, spec_mem_rmask)
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m.d.comb += self.spec_mem_rmask.eq(spec_mem_rmask)
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spec_mem_wmask = 0
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for _, insn in insn_submodules.items():
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spec_mem_wmask = Mux(insn.spec_valid, insn.spec_mem_wmask, spec_mem_wmask)
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m.d.comb += self.spec_mem_wmask.eq(spec_mem_wmask)
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spec_mem_wdata = 0
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for _, insn in insn_submodules.items():
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spec_mem_wdata = Mux(insn.spec_valid, insn.spec_mem_wdata, spec_mem_wdata)
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m.d.comb += self.spec_mem_wdata.eq(spec_mem_wdata)
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if self.params.csr_misa:
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spec_csr_misa_rmask = 0
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for _, insn in insn_submodules.items():
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spec_csr_misa_rmask = Mux(insn.spec_valid, insn.spec_csr_misa_rmask, spec_csr_misa_rmask)
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m.d.comb += self.spec_csr_misa_rmask.eq(spec_csr_misa_rmask)
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return m
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