2020-08-10 17:19:57 +08:00
|
|
|
from InsnRV32IITypeArith import *
|
|
|
|
|
|
2020-08-10 17:24:50 +08:00
|
|
|
"""
|
|
|
|
|
ADDI instruction
|
|
|
|
|
"""
|
|
|
|
|
|
2020-08-10 17:19:57 +08:00
|
|
|
class InsnAddi(InsnRV32IITypeArith):
|
|
|
|
|
def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED):
|
|
|
|
|
super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b000)
|
|
|
|
|
def elaborate(self, platform):
|
|
|
|
|
m = super().elaborate(platform)
|
|
|
|
|
|
|
|
|
|
m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_rs1_rdata + self.insn_imm, 0))
|
|
|
|
|
|
|
|
|
|
return m
|
