2020-08-07 13:45:35 +08:00
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from Insn import *
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"""
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RV32I R-Type Instruction
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"""
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class InsnRV32IRType(Insn):
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2020-08-12 13:19:13 +08:00
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def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, funct7, funct3, opcode):
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super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA)
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2020-08-07 13:45:35 +08:00
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self.funct7 = funct7
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self.funct3 = funct3
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self.opcode = opcode
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def elaborate(self, platform):
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2020-08-10 11:15:05 +08:00
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m = super().elaborate(platform)
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2020-08-07 13:45:35 +08:00
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if self.RISCV_FORMAL_CSR_MISA:
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m.d.comb += self.misa_ok.eq((self.rvfi_csr_misa_rdata & 0) == 0)
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m.d.comb += self.spec_csr_misa_rmask.eq(0)
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else:
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m.d.comb += self.misa_ok.eq(1)
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m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == self.funct7) & (self.insn_funct3 == self.funct3) & (self.insn_opcode == self.opcode))
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m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
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m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2)
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m.d.comb += self.spec_rd_addr.eq(self.insn_rd)
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m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
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return m
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