26 lines
1.0 KiB
Python
26 lines
1.0 KiB
Python
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from insn_I import *
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class rvfi_insn_lw(rvfi_insn_I):
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def __init__(self):
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super(rvfi_insn_lw, self).__init__()
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def ports(self):
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return super(rvfi_insn_lw, self).ports()
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def elaborate(self, platform):
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m = super(rvfi_insn_lw, self).elaborate(platform)
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# LW instruction
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addr = Signal(32)
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m.d.comb += addr.eq(self.rvfi_rs1_rdata + self.insn_imm)
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result = Signal(32)
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m.d.comb += result.eq(self.rvfi_mem_rdata)
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m.d.comb += self.spec_valid.eq(self.rvfi_valid & (self.insn_funct3 == 0b010) & (self.insn_opcode == 0b0000011))
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m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
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m.d.comb += self.spec_rd_addr.eq(self.insn_rd)
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m.d.comb += self.spec_mem_addr.eq(addr)
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m.d.comb += self.spec_mem_rmask.eq((1 << 4) - 1)
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m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, Value.as_signed(result), 0))
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m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
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m.d.comb += self.spec_trap.eq(~self.misa_ok)
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return m
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