47 lines
2.5 KiB
Python
47 lines
2.5 KiB
Python
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from Insn import *
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"""
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RV32I S-Type Instruction
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"""
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class InsnRV32ISType(Insn):
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def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, RISCV_FORMAL_ALIGNED_MEM, funct3, mask_shift):
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super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED)
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self.RISCV_FORMAL_ALIGNED_MEM = RISCV_FORMAL_ALIGNED_MEM
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self.funct3 = funct3
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self.mask_shift = mask_shift
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self.addr = Signal(self.RISCV_FORMAL_XLEN)
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def elaborate(self, platform):
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m = super().elaborate(platform)
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m.d.comb += self.insn_imm.eq(Value.as_signed(Cat(self.rvfi_insn[7:12], self.rvfi_insn[25:32])))
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if self.RISCV_FORMAL_CSR_MISA:
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m.d.comb += self.misa_ok.eq((self.rvfi_csr_misa_rdata & 0) == 0)
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m.d.comb += self.spec_csr_misa_rmask.eq(0)
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else:
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m.d.comb += self.misa_ok.eq(1)
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if self.RISCV_FORMAL_ALIGNED_MEM:
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m.d.comb += self.addr.eq(self.rvfi_rs1_rdata + self.insn_imm)
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m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == self.funct3) & (self.insn_opcode == 0b0100011))
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m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
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m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2)
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m.d.comb += self.spec_mem_addr.eq(self.addr & ~(int(self.RISCV_FORMAL_XLEN // 8) - 1))
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m.d.comb += self.spec_mem_wmask.eq(((1 << self.mask_shift) - 1) << (self.addr - self.spec_mem_addr))
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m.d.comb += self.spec_mem_wdata.eq(self.rvfi_rs2_rdata << (8 * (self.addr - self.spec_mem_addr)))
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m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
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m.d.comb += self.spec_trap.eq(((self.addr & (self.mask_shift - 1)) != 0) | ~self.misa_ok)
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else:
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m.d.comb += self.addr.eq(self.rvfi_rs1_rdata + self.insn_imm)
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m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == self.funct3) & (self.insn_opcode == 0b0100011))
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m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
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m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2)
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m.d.comb += self.spec_mem_addr.eq(self.addr)
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m.d.comb += self.spec_mem_wmask.eq((1 << self.mask_shift) - 1)
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m.d.comb += self.spec_mem_wdata.eq(self.rvfi_rs2_rdata)
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m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
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m.d.comb += self.spec_trap.eq(~self.misa_ok)
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return m
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