32 lines
1.3 KiB
Python
32 lines
1.3 KiB
Python
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from Insn import *
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"""
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RV32I SB-Type Instruction
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"""
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class InsnRV32ISBType(Insn):
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def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, funct3):
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super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED)
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self.funct3 = funct3
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def elaborate(self, platform):
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m = super().elaborate(platform)
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m.d.comb += self.insn_imm.eq(Value.as_signed(Cat(self.rvfi_insn[8:12], self.rvfi_insn[25:31], self.rvfi_insn[7], self.rvfi_insn[31]) << 1))
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if self.RISCV_FORMAL_CSR_MISA:
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m.d.comb += self.misa_ok.eq((self.rvfi_csr_misa_rdata & 0) == 0)
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m.d.comb += self.spec_csr_misa_rmask.eq(4)
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m.d.comb += self.ialign16.eq((self.rvfi_csr_misa_rdata & 4) != 0)
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else:
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m.d.comb += self.misa_ok.eq(1)
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if self.RISCV_FORMAL_COMPRESSED:
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m.d.comb += self.ialign16.eq(1)
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else:
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m.d.comb += self.ialign16.eq(0)
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m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == self.funct3) & (self.insn_opcode == 0b1100011))
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m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
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m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2)
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return m
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