riscv-formal-nmigen/insns/InsnAuipc.py

16 lines
471 B
Python
Raw Normal View History

2020-08-11 17:32:56 +08:00
from InsnRV32IUType import *
"""
AUIPC instruction
"""
class InsnAuipc(InsnRV32IUType):
def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA):
super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, 0b0010111)
2020-08-11 17:32:56 +08:00
def elaborate(self, platform):
m = super().elaborate(platform)
m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_pc_rdata + self.insn_imm, 0))
return m