2020-08-10 12:35:49 +08:00
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from InsnRV32IITypeShift import *
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"""
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SRLI instruction
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"""
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class InsnSrli(InsnRV32IITypeShift):
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2020-08-12 13:37:54 +08:00
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def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA):
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super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, 0b000000, 0b101)
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2020-08-10 12:35:49 +08:00
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def elaborate(self, platform):
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m = super().elaborate(platform)
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m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_rs1_rdata >> self.insn_shamt, 0))
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return m
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