riscv-formal-nmigen/insns/InsnSltiu.py

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2020-08-10 17:29:55 +08:00
from InsnRV32IITypeArith import *
"""
SLTIU instruction
"""
class InsnSltiu(InsnRV32IITypeArith):
def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA):
super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, 0b011)
2020-08-10 17:29:55 +08:00
def elaborate(self, platform):
m = super().elaborate(platform)
m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_rs1_rdata < self.insn_imm, 0))
return m