riscv-formal-nmigen/insns/insn_auipc.py

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from insn_U_type import *
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class rvfi_insn_auipc(rvfi_insn_U_type):
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def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
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super(rvfi_insn_auipc, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN)
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def ports(self):
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return super(rvfi_insn_auipc, self).ports()
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def elaborate(self, platform):
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m = super(rvfi_insn_auipc, self).elaborate(platform)
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# LUI instruction
m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_opcode == 0b0010111))
m.d.comb += self.spec_rd_addr.eq(self.insn_rd)
m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_pc_rdata + self.insn_imm, 0))
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m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
return m