141 lines
5.1 KiB
Python
141 lines
5.1 KiB
Python
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import warnings
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from ..._utils import deprecated, extend
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from ...hdl.ast import *
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from ...hdl.ir import Elaboratable
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from ...hdl.mem import Memory as NativeMemory
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from ...hdl.ir import Fragment, Instance
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from ...hdl.dsl import Module
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from .module import Module as CompatModule
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from .structure import Signal
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from ...lib.io import Pin
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__all__ = ["TSTriple", "Instance", "Memory", "READ_FIRST", "WRITE_FIRST", "NO_CHANGE"]
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class TSTriple:
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def __init__(self, bits_sign=None, min=None, max=None, reset_o=0, reset_oe=0, reset_i=0,
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name=None):
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self.o = Signal(bits_sign, min=min, max=max, reset=reset_o,
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name=None if name is None else name + "_o")
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self.oe = Signal(reset=reset_oe,
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name=None if name is None else name + "_oe")
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self.i = Signal(bits_sign, min=min, max=max, reset=reset_i,
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name=None if name is None else name + "_i")
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def __len__(self):
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return len(self.o)
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def get_tristate(self, io):
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return Tristate(io, self.o, self.oe, self.i)
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class Tristate(Elaboratable):
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def __init__(self, target, o, oe, i=None):
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self.target = target
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self.o = o
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self.oe = oe
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self.i = i if i is not None else None
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def elaborate(self, platform):
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if hasattr(platform, "get_input_output"):
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pin = Pin(len(self.target), dir="oe" if self.i is None else "io")
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pin.o = self.o
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pin.oe = self.oe
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if self.i is not None:
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pin.i = self.i
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return platform.get_input_output(pin, self.target, attrs={}, invert=None)
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m = Module()
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m.d.comb += self.i.eq(self.target)
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m.submodules += Instance("$tribuf",
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p_WIDTH=len(self.target),
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i_EN=self.oe,
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i_A=self.o,
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o_Y=self.target,
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)
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f = m.elaborate(platform)
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f.flatten = True
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return f
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(READ_FIRST, WRITE_FIRST, NO_CHANGE) = range(3)
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class _MemoryPort(CompatModule):
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def __init__(self, adr, dat_r, we=None, dat_w=None, async_read=False, re=None,
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we_granularity=0, mode=WRITE_FIRST, clock_domain="sync"):
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self.adr = adr
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self.dat_r = dat_r
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self.we = we
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self.dat_w = dat_w
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self.async_read = async_read
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self.re = re
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self.we_granularity = we_granularity
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self.mode = mode
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self.clock = ClockSignal(clock_domain)
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@extend(NativeMemory)
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@deprecated("it is not necessary or permitted to add Memory as a special or submodule")
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def elaborate(self, platform):
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return Fragment()
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class CompatMemory(NativeMemory, Elaboratable):
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def __init__(self, width, depth, init=None, name=None):
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super().__init__(width=width, depth=depth, init=init, name=name)
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@deprecated("instead of `get_port()`, use `read_port()` and `write_port()`")
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def get_port(self, write_capable=False, async_read=False, has_re=False, we_granularity=0,
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mode=WRITE_FIRST, clock_domain="sync"):
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if we_granularity >= self.width:
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warnings.warn("do not specify `we_granularity` greater than memory width, as it "
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"is a hard error in non-compatibility mode",
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DeprecationWarning, stacklevel=1)
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we_granularity = 0
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if we_granularity == 0:
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warnings.warn("instead of `we_granularity=0`, use `we_granularity=None` or avoid "
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"specifying it at all, as it is a hard error in non-compatibility mode",
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DeprecationWarning, stacklevel=1)
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we_granularity = None
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assert mode != NO_CHANGE
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rdport = self.read_port(domain="comb" if async_read else clock_domain,
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transparent=mode == WRITE_FIRST)
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rdport.addr.name = "{}_addr".format(self.name)
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adr = rdport.addr
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dat_r = rdport.data
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if write_capable:
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wrport = self.write_port(domain=clock_domain, granularity=we_granularity)
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wrport.addr = rdport.addr
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we = wrport.en
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dat_w = wrport.data
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else:
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we = None
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dat_w = None
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if has_re:
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if mode == READ_FIRST:
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re = rdport.en
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else:
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warnings.warn("the combination of `has_re=True` and `mode=WRITE_FIRST` has "
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"surprising behavior: keeping `re` low would merely latch "
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"the address, while the data will change with changing memory "
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"contents; avoid using `re` with transparent ports as it is a hard "
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"error in non-compatibility mode",
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DeprecationWarning, stacklevel=1)
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re = Signal()
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else:
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re = None
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mp = _MemoryPort(adr, dat_r, we, dat_w,
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async_read, re, we_granularity, mode,
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clock_domain)
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mp.submodules.rdport = rdport
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if write_capable:
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mp.submodules.wrport = wrport
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return mp
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Memory = CompatMemory
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