riscv-formal-nmigen/insns/insn_srl.py

24 lines
993 B
Python
Raw Normal View History

2020-08-04 12:42:39 +08:00
from insn_R import *
class rvfi_insn_srl(rvfi_insn_R):
def __init__(self):
super(rvfi_insn_srl, self).__init__()
def ports(self):
return super(rvfi_insn_srl, self).ports()
def elaborate(self, platform):
m = super(rvfi_insn_srl, self).elaborate(platform)
# SRL instruction
shamt = Signal(6)
m.d.comb += shamt.eq(self.rvfi_rs2_rdata[:5])
result = Signal(32)
m.d.comb += result.eq(self.rvfi_rs1_rdata >> shamt)
m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0000000) & (self.insn_funct3 == 0b101) & (self.insn_opcode == 0b0110011))
m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2)
m.d.comb += self.spec_rd_addr.eq(self.insn_rd)
m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0))
m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
return m