riscv-formal-nmigen/insns/InsnLw.py

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2020-08-10 16:35:37 +08:00
from InsnRV32IITypeLoad import *
"""
LW instruction
"""
class InsnLw(InsnRV32IITypeLoad):
def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_ALIGNED_MEM):
super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_ALIGNED_MEM, 0b010, 4, True)