gateware: add cdc fifo for dac output value override csr
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87059eef2b
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@ -39,14 +39,19 @@ class DAC(Module, AutoCSR):
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output_data_ch1 = Signal(14)
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self.data_in = [Signal(14, reset_less=True), Signal(14, reset_less=True)]
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self.data_in_csr = [Signal(14, reset_less=True), Signal(14, reset_less=True)]
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self.data_in_cdc = [Signal(14, reset_less=True), Signal(14, reset_less=True)]
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self.data_in_csr_cdc = [Signal(14, reset_less=True), Signal(14, reset_less=True)]
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platform.add_period_constraint(dac_pads.dclkio, 10.0)
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self.submodules.cdc_fifo = ClockDomainsRenamer({"write": "sys", "read": "dco2d"})(AsyncFIFO([("data", 28)], 4))
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self.submodules.cdc_fifo = ClockDomainsRenamer({"write": "sys", "read": "dco2d"})(AsyncFIFO([("data", 56)], 4))
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self.comb += [
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self.cdc_fifo.sink.data.eq(Cat(self.data_in[0], self.data_in[1])),
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self.data_in_csr[0].eq(self.output_value_ch0.storage),
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self.data_in_csr[1].eq(self.output_value_ch1.storage),
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self.cdc_fifo.sink.data.eq(Cat(self.data_in[0], self.data_in[1], self.data_in_csr[0], self.data_in_csr[1])),
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self.cdc_fifo.sink.stb.eq(~ResetSignal("sys")),
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Cat(self.data_in_cdc[0], self.data_in_cdc[1]).eq(self.cdc_fifo.source.data),
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Cat(self.data_in_cdc[0], self.data_in_cdc[1], self.data_in_csr_cdc[0], self.data_in_csr_cdc[1]).eq(self.cdc_fifo.source.data),
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self.cdc_fifo.source.ack.eq(~ResetSignal("dco2d")),
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]
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@ -56,10 +61,10 @@ class DAC(Module, AutoCSR):
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dac_afe_pads.ch1_pd_n.eq(~ch0_pd),
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dac_afe_pads.ch2_pd_n.eq(~ch1_pd),
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output_data_ch0.eq(
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Mux(manual_override, self.output_value_ch0.storage, self.data_in_cdc[0])
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Mux(manual_override, self.data_in_csr_cdc[0], self.data_in_cdc[0])
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),
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output_data_ch1.eq(
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Mux(manual_override, self.output_value_ch1.storage, self.data_in_cdc[1])
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Mux(manual_override, self.data_in_csr_cdc[1], self.data_in_cdc[1])
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),
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]
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