diff --git a/fast-servo/linien-gateware/cores/dac.py b/fast-servo/linien-gateware/cores/dac.py
index 26cd3d9..df4c3b8 100644
--- a/fast-servo/linien-gateware/cores/dac.py
+++ b/fast-servo/linien-gateware/cores/dac.py
@@ -39,14 +39,19 @@ class DAC(Module, AutoCSR):
         output_data_ch1 = Signal(14)
 
         self.data_in = [Signal(14, reset_less=True), Signal(14, reset_less=True)]
+        self.data_in_csr = [Signal(14, reset_less=True), Signal(14, reset_less=True)]
+        
         self.data_in_cdc = [Signal(14, reset_less=True), Signal(14, reset_less=True)]
+        self.data_in_csr_cdc = [Signal(14, reset_less=True), Signal(14, reset_less=True)]
         platform.add_period_constraint(dac_pads.dclkio, 10.0)
 
-        self.submodules.cdc_fifo = ClockDomainsRenamer({"write": "sys", "read": "dco2d"})(AsyncFIFO([("data", 28)], 4))
+        self.submodules.cdc_fifo = ClockDomainsRenamer({"write": "sys", "read": "dco2d"})(AsyncFIFO([("data", 56)], 4))
         self.comb += [
-            self.cdc_fifo.sink.data.eq(Cat(self.data_in[0], self.data_in[1])),
+            self.data_in_csr[0].eq(self.output_value_ch0.storage), 
+            self.data_in_csr[1].eq(self.output_value_ch1.storage),
+            self.cdc_fifo.sink.data.eq(Cat(self.data_in[0], self.data_in[1], self.data_in_csr[0], self.data_in_csr[1])),
             self.cdc_fifo.sink.stb.eq(~ResetSignal("sys")),
-            Cat(self.data_in_cdc[0], self.data_in_cdc[1]).eq(self.cdc_fifo.source.data),
+            Cat(self.data_in_cdc[0], self.data_in_cdc[1], self.data_in_csr_cdc[0], self.data_in_csr_cdc[1]).eq(self.cdc_fifo.source.data),
             self.cdc_fifo.source.ack.eq(~ResetSignal("dco2d")),
         ]
 
@@ -56,10 +61,10 @@ class DAC(Module, AutoCSR):
             dac_afe_pads.ch1_pd_n.eq(~ch0_pd),
             dac_afe_pads.ch2_pd_n.eq(~ch1_pd),
             output_data_ch0.eq(
-                Mux(manual_override, self.output_value_ch0.storage, self.data_in_cdc[0])
+                Mux(manual_override, self.data_in_csr_cdc[0], self.data_in_cdc[0])
             ),
             output_data_ch1.eq(
-                Mux(manual_override, self.output_value_ch1.storage, self.data_in_cdc[1])
+                Mux(manual_override, self.data_in_csr_cdc[1], self.data_in_cdc[1])
             ),
         ]