pyfastservo dac: reacquire clk relationship at init
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@ -63,7 +63,10 @@ def configure_dac(spi):
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spi_write(spi, 0x07, 0xA0) # Enable on-chip QRSET (1.6 kΩ for 20mA output)
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spi_write(spi, 0x07, 0xA0) # Enable on-chip QRSET (1.6 kΩ for 20mA output)
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spi_write(spi, 0x05, 0x00) # Disable internal IRCML
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spi_write(spi, 0x05, 0x00) # Disable internal IRCML
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spi_write(spi, 0x08, 0x00) # Disable internal QRCML
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spi_write(spi, 0x08, 0x00) # Disable internal QRCML
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spi_write(spi, 0x02, 0xB4) # Enable 2's complement, LVDS interface, 4 LVDS lanes
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spi_write(spi, 0x02, 0xB4) # Enable 2's complement, IFirst: True, IRising: True, DCI_EN: Enabled
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spi_write(spi, 0x14, 0x00)
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spi_write(spi, 0x14, 0x08) # Trigger the retimer to reacquire the clock relationship
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spi_write(spi, 0x14, 0x00)
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def dac_self_calibration(spi):
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def dac_self_calibration(spi):
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spi_write(spi, 0x12, 0x00) # Reset calibration status
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spi_write(spi, 0x12, 0x00) # Reset calibration status
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@ -111,6 +114,16 @@ def set_dac_output(value):
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write_to_memory(CH1_LOW_WORD_ADDR, low_word)
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write_to_memory(CH1_LOW_WORD_ADDR, low_word)
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print(f"DAC output set to: 0x{value:04X}")
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print(f"DAC output set to: 0x{value:04X}")
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def check_clk_relationship(spi):
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clkmode_reg = spi_read(spi, 0x14)
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print(f"CLKMODE reg: 0x{clkmode_reg:02X}")
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if clkmode_reg & 0b00010000:
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print("Clock relationship is not found")
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return False
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else:
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print("Clock relationship is found")
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return True
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def configure_ad9117():
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def configure_ad9117():
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spi = spidev.SpiDev()
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spi = spidev.SpiDev()
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spi.open(MAIN_DAC_BUS, MAIN_DAC_DEVICE)
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spi.open(MAIN_DAC_BUS, MAIN_DAC_DEVICE)
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@ -125,6 +138,7 @@ def configure_ad9117():
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return False
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return False
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configure_dac(spi)
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configure_dac(spi)
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check_clk_relationship(spi)
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dac_self_calibration(spi)
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dac_self_calibration(spi)
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# Enable DAC outputs
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# Enable DAC outputs
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