58 lines
2.4 KiB
Diff
58 lines
2.4 KiB
Diff
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diff --git a/gateware/linien_module.py b/gateware/linien_module.py
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index a958896..a64714c 100644
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--- a/gateware/linien_module.py
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+++ b/gateware/linien_module.py
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@@ -233,23 +233,46 @@ class LinienModule(Module, AutoCSR):
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self.fast_a.adc.eq(soc.analog.adc_a),
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self.fast_b.adc.eq(soc.analog.adc_b),
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]
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-
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+
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# now, we combine the output of the two paths, with a variable factor each.
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mixed = Signal(
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(2 + ((signal_width + 1) + self.logic.chain_a_factor.size), True)
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)
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+
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+ chain_a_factor_mult_fast_a_out_i = Signal(
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+ (2 + ((signal_width + 1) + self.logic.chain_a_factor.size), True)
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+ )
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+
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+ chain_b_factor_mult_fast_b_out_i = Signal(
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+ (2 + ((signal_width + 1) + self.logic.chain_a_factor.size), True)
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+ )
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+ combined_offset_signed_left_shifted = Signal(
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+ (2 + ((signal_width + 1) + self.logic.chain_a_factor.size), True)
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+ )
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+ fast_a_out_i_left_shifted = Signal(
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+ (2 + ((signal_width + 1) + self.logic.chain_a_factor.size), True)
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+ )
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+
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+ self.sync += [
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+ chain_a_factor_mult_fast_a_out_i.eq(self.logic.chain_a_factor.storage * self.fast_a.out_i),
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+ chain_b_factor_mult_fast_b_out_i.eq(self.logic.chain_b_factor.storage * self.fast_b.out_i),
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+ combined_offset_signed_left_shifted.eq(self.logic.combined_offset_signed << (chain_factor_bits + s)),
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+ fast_a_out_i_left_shifted.eq(self.fast_a.out_i << chain_factor_bits),
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+ ]
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+
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+
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self.comb += [
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If(
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self.logic.dual_channel.storage,
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mixed.eq(
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- (self.logic.chain_a_factor.storage * self.fast_a.out_i)
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- + (self.logic.chain_b_factor.storage * self.fast_b.out_i)
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- + (self.logic.combined_offset_signed << (chain_factor_bits + s))
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+ chain_a_factor_mult_fast_a_out_i
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+ + chain_b_factor_mult_fast_b_out_i
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+ + combined_offset_signed_left_shifted
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),
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).Else(
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mixed.eq(
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- (self.fast_a.out_i << chain_factor_bits)
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- + (self.logic.combined_offset_signed << (chain_factor_bits + s))
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+ fast_a_out_i_left_shifted
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+ + combined_offset_signed_left_shifted
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)
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)
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]
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