diff --git a/gateware/linien_module.py b/gateware/linien_module.py
index a958896..a64714c 100644
--- a/gateware/linien_module.py
+++ b/gateware/linien_module.py
@@ -233,23 +233,46 @@ class LinienModule(Module, AutoCSR):
             self.fast_a.adc.eq(soc.analog.adc_a),
             self.fast_b.adc.eq(soc.analog.adc_b),
         ]
-
+        
         # now, we combine the output of the two paths, with a variable factor each.
         mixed = Signal(
             (2 + ((signal_width + 1) + self.logic.chain_a_factor.size), True)
         )
+
+        chain_a_factor_mult_fast_a_out_i = Signal(
+            (2 + ((signal_width + 1) + self.logic.chain_a_factor.size), True)
+        )
+
+        chain_b_factor_mult_fast_b_out_i = Signal(
+            (2 + ((signal_width + 1) + self.logic.chain_a_factor.size), True)
+        )
+        combined_offset_signed_left_shifted = Signal(
+            (2 + ((signal_width + 1) + self.logic.chain_a_factor.size), True)
+        )
+        fast_a_out_i_left_shifted = Signal(
+            (2 + ((signal_width + 1) + self.logic.chain_a_factor.size), True)
+        )
+
+        self.sync += [
+            chain_a_factor_mult_fast_a_out_i.eq(self.logic.chain_a_factor.storage * self.fast_a.out_i),
+            chain_b_factor_mult_fast_b_out_i.eq(self.logic.chain_b_factor.storage * self.fast_b.out_i),
+            combined_offset_signed_left_shifted.eq(self.logic.combined_offset_signed << (chain_factor_bits + s)),
+            fast_a_out_i_left_shifted.eq(self.fast_a.out_i << chain_factor_bits),
+        ] 
+
+
         self.comb += [
             If(
                 self.logic.dual_channel.storage,
                 mixed.eq(
-                    (self.logic.chain_a_factor.storage * self.fast_a.out_i)
-                    + (self.logic.chain_b_factor.storage * self.fast_b.out_i)
-                    + (self.logic.combined_offset_signed << (chain_factor_bits + s))
+                    chain_a_factor_mult_fast_a_out_i
+                    + chain_b_factor_mult_fast_b_out_i
+                    + combined_offset_signed_left_shifted
                 ),
             ).Else(
                 mixed.eq(
-                    (self.fast_a.out_i << chain_factor_bits)
-                    + (self.logic.combined_offset_signed << (chain_factor_bits + s))
+                    fast_a_out_i_left_shifted
+                    + combined_offset_signed_left_shifted
                 )
             )
         ]