M-Labs/nac3
M-Labs/nac3
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core: Remove emit_llvm from CodeGenLLVMOptions

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We instead output an LLVM bitcode file when the option is specified on
the command-line.
This commit is contained in:
David Mak 2023-09-15 13:26:15 +08:00
parent ee1ee4ab3b
commit ab2360d7a0
4 changed files with 9 additions and 13 deletions
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1
nac3artiq/src/lib.rs
View File

@ -916,7 +916,6 @@ impl Nac3 {
llvm_options: CodeGenLLVMOptions { llvm_options: CodeGenLLVMOptions {
opt_level: OptimizationLevel::Default, opt_level: OptimizationLevel::Default,
target: Nac3::get_llvm_target_options(isa), target: Nac3::get_llvm_target_options(isa),
emit_llvm: false,
} }
}) })
} }

8
nac3core/src/codegen/mod.rs
View File

@ -61,9 +61,6 @@ pub struct CodeGenLLVMOptions {
/// Options related to the target machine. /// Options related to the target machine.
pub target: CodeGenTargetMachineOptions, pub target: CodeGenTargetMachineOptions,
/// Whether to output the LLVM IR after generation is complete.
pub emit_llvm: bool,
} }
/// Additional options for code generation for the target machine. /// Additional options for code generation for the target machine.
@ -339,11 +336,6 @@ impl WorkerRegistry {
err.to_string()); err.to_string());
} }
if self.llvm_options.emit_llvm {
println!("LLVM IR for {}\n{}", module.get_name().to_str().unwrap(), module.to_string());
println!();
}
f.run(&module); f.run(&module);
let mut lock = self.task_count.lock(); let mut lock = self.task_count.lock();
*lock += 1; *lock += 1;

2
nac3core/src/codegen/test.rs
View File

@ -222,7 +222,6 @@ fn test_primitives() {
let llvm_options = CodeGenLLVMOptions { let llvm_options = CodeGenLLVMOptions {
opt_level: OptimizationLevel::Default, opt_level: OptimizationLevel::Default,
target: CodeGenTargetMachineOptions::from_host_triple(), target: CodeGenTargetMachineOptions::from_host_triple(),
emit_llvm: false,
}; };
let (registry, handles) = WorkerRegistry::create_workers( let (registry, handles) = WorkerRegistry::create_workers(
threads, threads,
@ -413,7 +412,6 @@ fn test_simple_call() {
let llvm_options = CodeGenLLVMOptions { let llvm_options = CodeGenLLVMOptions {
opt_level: OptimizationLevel::Default, opt_level: OptimizationLevel::Default,
target: CodeGenTargetMachineOptions::from_host_triple(), target: CodeGenTargetMachineOptions::from_host_triple(),
emit_llvm: false,
}; };
let (registry, handles) = WorkerRegistry::create_workers( let (registry, handles) = WorkerRegistry::create_workers(
threads, threads,

11
nac3standalone/src/main.rs
View File

@ -305,7 +305,6 @@ fn main() {
features: target_features, features: target_features,
..host_target_machine ..host_target_machine
}, },
emit_llvm,
}; };
let task = CodeGenTask { let task = CodeGenTask {
@ -340,11 +339,19 @@ fn main() {
let main = context let main = context
.create_module_from_ir(MemoryBuffer::create_from_memory_range(&buffers[0], "main")) .create_module_from_ir(MemoryBuffer::create_from_memory_range(&buffers[0], "main"))
.unwrap(); .unwrap();
for buffer in buffers.iter().skip(1) { if emit_llvm {
main.write_bitcode_to_path(Path::new("main.bc"));
}
for (idx, buffer) in buffers.iter().skip(1).enumerate() {
let other = context let other = context
.create_module_from_ir(MemoryBuffer::create_from_memory_range(buffer, "main")) .create_module_from_ir(MemoryBuffer::create_from_memory_range(buffer, "main"))
.unwrap(); .unwrap();
if emit_llvm {
other.write_bitcode_to_path(Path::new(&format!("module{}.bc", idx)));
}
main.link_in_module(other).unwrap(); main.link_in_module(other).unwrap();
} }
main.link_in_module(load_irrt(&context)).unwrap(); main.link_in_module(load_irrt(&context)).unwrap();