From ab2360d7a0950d7b5e7434c9e2c26d6ec1b2cf80 Mon Sep 17 00:00:00 2001
From: David Mak <csdavidmak@ust.hk>
Date: Fri, 15 Sep 2023 13:26:15 +0800
Subject: [PATCH] core: Remove emit_llvm from CodeGenLLVMOptions

We instead output an LLVM bitcode file when the option is specified on
the command-line.
---
 nac3artiq/src/lib.rs         |  1 -
 nac3core/src/codegen/mod.rs  |  8 --------
 nac3core/src/codegen/test.rs |  2 --
 nac3standalone/src/main.rs   | 11 +++++++++--
 4 files changed, 9 insertions(+), 13 deletions(-)

diff --git a/nac3artiq/src/lib.rs b/nac3artiq/src/lib.rs
index 80f8222..18eeb5d 100644
--- a/nac3artiq/src/lib.rs
+++ b/nac3artiq/src/lib.rs
@@ -916,7 +916,6 @@ impl Nac3 {
             llvm_options: CodeGenLLVMOptions {
                 opt_level: OptimizationLevel::Default,
                 target: Nac3::get_llvm_target_options(isa),
-                emit_llvm: false,
             }
         })
     }
diff --git a/nac3core/src/codegen/mod.rs b/nac3core/src/codegen/mod.rs
index 0d8e3c8..a315f76 100644
--- a/nac3core/src/codegen/mod.rs
+++ b/nac3core/src/codegen/mod.rs
@@ -61,9 +61,6 @@ pub struct CodeGenLLVMOptions {
 
     /// Options related to the target machine.
     pub target: CodeGenTargetMachineOptions,
-
-    /// Whether to output the LLVM IR after generation is complete.
-    pub emit_llvm: bool,
 }
 
 /// Additional options for code generation for the target machine.
@@ -339,11 +336,6 @@ impl WorkerRegistry {
                    err.to_string());
         }
 
-        if self.llvm_options.emit_llvm {
-            println!("LLVM IR for {}\n{}", module.get_name().to_str().unwrap(), module.to_string());
-            println!();
-        }
-
         f.run(&module);
         let mut lock = self.task_count.lock();
         *lock += 1;
diff --git a/nac3core/src/codegen/test.rs b/nac3core/src/codegen/test.rs
index df8c02a..6daf50e 100644
--- a/nac3core/src/codegen/test.rs
+++ b/nac3core/src/codegen/test.rs
@@ -222,7 +222,6 @@ fn test_primitives() {
     let llvm_options = CodeGenLLVMOptions {
         opt_level: OptimizationLevel::Default,
         target: CodeGenTargetMachineOptions::from_host_triple(),
-        emit_llvm: false,
     };
     let (registry, handles) = WorkerRegistry::create_workers(
         threads,
@@ -413,7 +412,6 @@ fn test_simple_call() {
     let llvm_options = CodeGenLLVMOptions {
         opt_level: OptimizationLevel::Default,
         target: CodeGenTargetMachineOptions::from_host_triple(),
-        emit_llvm: false,
     };
     let (registry, handles) = WorkerRegistry::create_workers(
         threads,
diff --git a/nac3standalone/src/main.rs b/nac3standalone/src/main.rs
index f1a2160..d45b875 100644
--- a/nac3standalone/src/main.rs
+++ b/nac3standalone/src/main.rs
@@ -305,7 +305,6 @@ fn main() {
             features: target_features,
             ..host_target_machine
         },
-        emit_llvm,
     };
 
     let task = CodeGenTask {
@@ -340,11 +339,19 @@ fn main() {
     let main = context
         .create_module_from_ir(MemoryBuffer::create_from_memory_range(&buffers[0], "main"))
         .unwrap();
-    for buffer in buffers.iter().skip(1) {
+    if emit_llvm {
+        main.write_bitcode_to_path(Path::new("main.bc"));
+    }
+
+    for (idx, buffer) in buffers.iter().skip(1).enumerate() {
         let other = context
             .create_module_from_ir(MemoryBuffer::create_from_memory_range(buffer, "main"))
             .unwrap();
 
+        if emit_llvm {
+            other.write_bitcode_to_path(Path::new(&format!("module{}.bc", idx)));
+        }
+
         main.link_in_module(other).unwrap();
     }
     main.link_in_module(load_irrt(&context)).unwrap();