2024-01-16 16:18:39 +08:00
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use core::fmt;
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use log::{info, warn};
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use stm32f4xx_hal::
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{
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spi::Spi,
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pac::SPI3,
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gpio::{PA15, Output, PushPull},
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hal::{
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spi::SpiBus,
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digital::OutputPin,
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},
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};
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use uom::si::{
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f32::ElectricPotential,
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electric_potential::volt,
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};
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use super::{
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checksum::{Checksum, ChecksumMode}, regs::{self, Register, RegisterData}, sinc3_fine_odr_closest, sinc3_fine_odr_output_rate, DigitalFilterOrder, FilterType, Input, Mode, PostFilter, RefSource, SingleChODR
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};
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/// AD7172-2 implementation
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///
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/// [Manual](https://www.analog.com/media/en/technical-documentation/data-sheets/AD7172-2.pdf)
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pub struct Adc<SPI: SpiBus<u8>, NSS: OutputPin> {
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spi: SPI,
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nss: NSS,
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checksum_mode: ChecksumMode,
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}
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type AdcSpi = Spi<SPI3>;
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type AdcNss = PA15<Output<PushPull>>;
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pub type AdcPhy = Adc<AdcSpi, AdcNss>;
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impl<SPI: SpiBus<u8, Error = E>, NSS: OutputPin, E: fmt::Debug> Adc<SPI, NSS> {
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pub fn new(spi: SPI, mut nss: NSS) -> Result<Self, SPI::Error> {
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let _ = nss.set_high();
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let mut adc = Adc {
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spi, nss,
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checksum_mode: ChecksumMode::Off,
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};
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adc.reset()?;
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adc.set_checksum_mode(ChecksumMode::Crc).unwrap();
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let mut retries = 0;
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let mut adc_id;
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loop {
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adc_id = adc.identify()?;
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if adc_id & 0xFFF0 == 0x00D0 {
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break;
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} else {
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retries += 1;
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}
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}
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info!("ADC id: {:04X} ({} retries)", adc_id, retries);
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let mut adc_mode = <regs::AdcMode as Register>::Data::empty();
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adc_mode.set_ref_en(true);
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adc_mode.set_sing_cyc(false);
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adc_mode.set_mode(Mode::Standby);
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adc.write_reg(®s::AdcMode, &mut adc_mode)?;
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Ok(adc)
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}
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/// `0x00DX` for AD7172-2
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pub fn identify(&mut self) -> Result<u16, SPI::Error> {
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self.read_reg(®s::Id)
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.map(|id| id.id())
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}
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pub fn set_checksum_mode(&mut self, mode: ChecksumMode) -> Result<(), SPI::Error> {
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// Cannot use update_reg() here because checksum_mode is
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// updated between read_reg() and write_reg().
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let mut ifmode = self.read_reg(®s::IfMode)?;
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ifmode.set_crc(mode);
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self.checksum_mode = mode;
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self.write_reg(®s::IfMode, &mut ifmode)?;
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Ok(())
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}
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pub fn set_sync_enable(&mut self, enable: bool) -> Result<(), SPI::Error> {
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self.update_reg(®s::GpioCon, |data| {
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data.set_sync_en(enable);
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})
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}
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pub fn setup_channel(
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&mut self, index: u8, in_pos: Input, in_neg: Input
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) -> Result<(), SPI::Error> {
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self.update_reg(®s::SetupCon { index }, |data| {
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data.set_bipolar(false);
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data.set_refbuf_pos(true);
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data.set_refbuf_neg(true);
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data.set_ainbuf_pos(true);
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data.set_ainbuf_neg(true);
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data.set_ref_sel(RefSource::External);
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})?;
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self.set_sinc5_sinc1_with_50hz_60hz_rejection(index, PostFilter::F16SPS)?;
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self.update_reg(®s::Channel { index }, |data| {
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data.set_setup(index);
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data.set_enabled(true);
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data.set_a_in_pos(in_pos);
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data.set_a_in_neg(in_neg);
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})?;
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Ok(())
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}
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pub fn get_calibration(&mut self, index: u8) -> Result<ChannelCalibration, SPI::Error> {
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let offset = self.read_reg(®s::Offset { index })?.offset();
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let gain = self.read_reg(®s::Gain { index })?.gain();
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let bipolar = self.read_reg(®s::SetupCon { index })?.bipolar();
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Ok(ChannelCalibration { offset, gain, bipolar })
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}
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pub fn start_continuous_conversion(&mut self) -> Result<(), SPI::Error> {
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let mut adc_mode = <regs::AdcMode as Register>::Data::empty();
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adc_mode.set_ref_en(true);
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// Set SING_CYC = 0 to maximize sampling rate with lowest noise for single channel of temperature measurement
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adc_mode.set_sing_cyc(false);
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adc_mode.set_mode(Mode::ContinuousConversion);
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self.write_reg(®s::AdcMode, &mut adc_mode)?;
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Ok(())
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}
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/// Rate is only valid with single channel enabled
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pub fn get_filter_type_and_rate(&mut self, index: u8) -> Result<(FilterType, f32), SPI::Error> {
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let mut filter_type: FilterType = FilterType::Sinc5Sinc1With50hz60HzRejection;
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let mut rate: f32 = -1.0;
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self.read_reg(®s::FiltCon { index })
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.map(|data| {
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if data.sinc3_map() {
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filter_type = FilterType::Sinc3WithFineODR;
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let odr : u16 = (data.sinc3_map_fine_odr_msb() as u16) << 8 | data.sinc3_map_fine_odr_lsb() as u16;
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rate = sinc3_fine_odr_output_rate(odr);
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} else if data.enh_filt_en() {
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filter_type = FilterType::Sinc5Sinc1With50hz60HzRejection;
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match data.enh_filt().output_rate(){
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Some(val) => { rate = val; }
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None => { rate = -1.0; }
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};
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} else if data.order() == DigitalFilterOrder::Sinc5Sinc1 {
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filter_type = FilterType::Sinc5Sinc1;
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match data.odr().output_rate(){
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Some(val) => { rate = val; }
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None => { rate = -1.0; }
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}
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} else {
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filter_type = FilterType::Sinc3;
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match data.odr().output_rate(){
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Some(val) => { rate = val; }
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None => { rate = -1.0; }
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}
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}
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})?;
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Ok((filter_type, rate))
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}
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pub fn set_sinc5_sinc1_with_50hz_60hz_rejection(&mut self, index: u8, rate: PostFilter) -> Result<(), SPI::Error> {
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self.update_reg(®s::FiltCon { index }, |data| {
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data.set_sinc3_map(false);
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data.set_enh_filt_en(true);
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data.set_order(DigitalFilterOrder::Sinc5Sinc1);
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data.set_enh_filt(rate);
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})
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}
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pub fn set_sinc5_sinc1_filter(&mut self, index: u8, rate: SingleChODR) -> Result<(), SPI::Error> {
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self.update_reg(®s::FiltCon { index }, |data| {
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data.set_sinc3_map(false);
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data.set_enh_filt_en(false);
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data.set_order(DigitalFilterOrder::Sinc5Sinc1);
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data.set_odr(rate);
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})
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}
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pub fn set_sinc3_filter(&mut self, index: u8, rate: SingleChODR) -> Result<(), SPI::Error> {
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self.update_reg(®s::FiltCon { index }, |data| {
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data.set_sinc3_map(false);
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data.set_enh_filt_en(false);
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data.set_order(DigitalFilterOrder::Sinc3);
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data.set_odr(rate);
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})
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}
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pub fn set_sinc3_fine_filter(&mut self, index: u8, rate: f32) -> Result<f32, SPI::Error> {
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let sinc3_fine_odr_u16 = sinc3_fine_odr_closest(rate);
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self.update_reg(®s::FiltCon { index }, |data| {
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data.set_sinc3_map(true);
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data.set_sinc3_map_fine_odr_msb((sinc3_fine_odr_u16 >> 8 & 0xFF) as u8);
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data.set_sinc3_map_fine_odr_lsb((sinc3_fine_odr_u16 & 0xFF) as u8);
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}).map(|_| sinc3_fine_odr_output_rate(sinc3_fine_odr_u16))
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}
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/// Returns the channel the data is from
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pub fn data_ready(&mut self) -> Result<Option<u8>, SPI::Error> {
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self.read_reg(®s::Status)
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.map(|status| {
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if status.ready() {
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Some(status.channel())
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} else {
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None
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}
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})
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}
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/// Get data
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pub fn read_data(&mut self) -> Result<u32, SPI::Error> {
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self.read_reg(®s::Data)
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.map(|data| data.data())
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}
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fn read_reg<R: regs::Register>(&mut self, reg: &R) -> Result<R::Data, SPI::Error> {
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let mut reg_data = R::Data::empty();
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let address = 0x40 | reg.address();
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let mut checksum = Checksum::new(self.checksum_mode);
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checksum.feed(&[address]);
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let checksum_out = checksum.result();
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loop {
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let checksum_in = self.transfer(address, reg_data.as_mut(), checksum_out)?;
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checksum.feed(®_data);
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let checksum_expected = checksum.result();
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if checksum_expected == checksum_in {
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break;
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}
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// Retry
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warn!("read_reg {:02X}: checksum error: {:?}!={:?}, retrying", reg.address(), checksum_expected, checksum_in);
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}
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Ok(reg_data)
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}
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fn write_reg<R: regs::Register>(&mut self, reg: &R, reg_data: &mut R::Data) -> Result<(), SPI::Error> {
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loop {
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let address = reg.address();
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let mut checksum = Checksum::new(match self.checksum_mode {
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ChecksumMode::Off => ChecksumMode::Off,
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// write checksums are always crc
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ChecksumMode::Xor => ChecksumMode::Crc,
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ChecksumMode::Crc => ChecksumMode::Crc,
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});
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checksum.feed(&[address]);
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checksum.feed(®_data);
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let checksum_out = checksum.result();
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let mut data = reg_data.clone();
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self.transfer(address, data.as_mut(), checksum_out)?;
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// Verification
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let readback_data = self.read_reg(reg)?;
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if *readback_data == **reg_data {
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return Ok(());
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}
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warn!("write_reg {:02X}: readback error, {:?}!={:?}, retrying", address, &*readback_data, &**reg_data);
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}
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}
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fn update_reg<R, F, A>(&mut self, reg: &R, f: F) -> Result<A, SPI::Error>
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where
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R: regs::Register,
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F: FnOnce(&mut R::Data) -> A,
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{
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let mut reg_data = self.read_reg(reg)?;
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let result = f(&mut reg_data);
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self.write_reg(reg, &mut reg_data)?;
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Ok(result)
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}
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pub fn reset(&mut self) -> Result<(), SPI::Error> {
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let mut buf = [0xFFu8; 8];
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let _ = self.nss.set_low();
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let result = self.spi.transfer_in_place(&mut buf);
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2024-01-16 16:18:39 +08:00
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let _ = self.nss.set_high();
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result?;
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Ok(())
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}
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fn transfer<'w>(&mut self, addr: u8, reg_data: &'w mut [u8], checksum: Option<u8>) -> Result<Option<u8>, SPI::Error> {
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let mut addr_buf = [addr];
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let _ = self.nss.set_low();
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let result = match self.spi.transfer_in_place(&mut addr_buf) {
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Ok(_) => self.spi.transfer_in_place(reg_data),
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Err(e) => Err(e),
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};
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let result = match (result, checksum) {
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(Ok(_), None) =>
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Ok(None),
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(Ok(_), Some(checksum_out)) => {
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let mut checksum_buf = [checksum_out; 1];
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match self.spi.transfer_in_place(&mut checksum_buf) {
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Ok(_) => Ok(Some(checksum_buf[0])),
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Err(e) => Err(e),
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}
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}
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(Err(e), _) =>
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Err(e),
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};
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let _ = self.nss.set_high();
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result
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}
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}
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#[derive(Debug, Clone)]
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pub struct ChannelCalibration {
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offset: u32,
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gain: u32,
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bipolar: bool,
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}
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2024-01-17 13:16:24 +08:00
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impl Default for ChannelCalibration {
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fn default() -> Self {
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ChannelCalibration {
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offset: 0,
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gain: 0,
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bipolar: false,
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}
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}
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}
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2024-01-16 16:18:39 +08:00
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impl ChannelCalibration {
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pub fn convert_data(&self, data: u32) -> ElectricPotential {
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let data = if self.bipolar {
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2024-02-27 16:26:05 +08:00
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(data as i32 - 0x80_0000) as f32
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2024-01-16 16:18:39 +08:00
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} else {
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2024-02-27 16:26:05 +08:00
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data as f32 / 2.0
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2024-01-16 16:18:39 +08:00
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};
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2024-02-27 16:26:05 +08:00
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let data = data / (self.gain as f32 / (0x40_0000 as f32));
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let data = data + (self.offset as i32 - 0x80_0000) as f32;
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let data = data / (2 << 23) as f32;
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2024-01-16 16:18:39 +08:00
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2024-02-27 16:26:05 +08:00
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const V_REF: f32 = 3.3;
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2024-01-16 16:18:39 +08:00
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ElectricPotential::new::<volt>(data * V_REF / 0.75)
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}
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}
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