parent
e355e83d28
commit
af8d361b95
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@ -366,6 +366,8 @@ name = "kirdy"
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version = "0.0.0"
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dependencies = [
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"bare-metal 1.0.0",
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"bit_field",
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"byteorder",
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"cortex-m",
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"cortex-m-log",
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"cortex-m-rt",
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@ -34,6 +34,8 @@ rtt-target = { version = "0.3.1", features = ["cortex-m"] }
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miniconf = "0.6.3"
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serde = { version = "1.0.158", features = ["derive"], default-features = false }
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sfkv = "0.1"
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bit_field = "0.10"
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byteorder = { version = "1", default-features = false }
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[features]
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semihosting = ["cortex-m-log/semihosting"]
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RTT = []
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@ -0,0 +1,276 @@
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use core::fmt;
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use log::{info, warn};
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use stm32f4xx_hal::hal::{
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blocking::spi::Transfer,
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digital::v2::OutputPin,
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};
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use uom::si::{
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f64::ElectricPotential,
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electric_potential::volt,
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};
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use super::{
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regs::{self, Register, RegisterData},
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checksum::{ChecksumMode, Checksum},
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Mode, Input, RefSource, PostFilter, DigitalFilterOrder,
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};
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/// AD7172-2 implementation
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///
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/// [Manual](https://www.analog.com/media/en/technical-documentation/data-sheets/AD7172-2.pdf)
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pub struct Adc<SPI: Transfer<u8>, NSS: OutputPin> {
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spi: SPI,
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nss: NSS,
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checksum_mode: ChecksumMode,
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}
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impl<SPI: Transfer<u8, Error = E>, NSS: OutputPin, E: fmt::Debug> Adc<SPI, NSS> {
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pub fn new(spi: SPI, mut nss: NSS) -> Result<Self, SPI::Error> {
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let _ = nss.set_high();
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let mut adc = Adc {
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spi, nss,
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checksum_mode: ChecksumMode::Off,
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};
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adc.reset()?;
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adc.set_checksum_mode(ChecksumMode::Crc).unwrap();
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let mut retries = 0;
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let mut adc_id;
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loop {
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adc_id = adc.identify()?;
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if adc_id & 0xFFF0 == 0x00D0 {
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break;
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} else {
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retries += 1;
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}
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}
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info!("ADC id: {:04X} ({} retries)", adc_id, retries);
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let mut adc_mode = <regs::AdcMode as Register>::Data::empty();
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adc_mode.set_ref_en(true);
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adc_mode.set_mode(Mode::Standby);
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adc.write_reg(®s::AdcMode, &mut adc_mode)?;
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Ok(adc)
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}
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/// `0x00DX` for AD7172-2
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pub fn identify(&mut self) -> Result<u16, SPI::Error> {
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self.read_reg(®s::Id)
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.map(|id| id.id())
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}
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pub fn set_checksum_mode(&mut self, mode: ChecksumMode) -> Result<(), SPI::Error> {
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// Cannot use update_reg() here because checksum_mode is
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// updated between read_reg() and write_reg().
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let mut ifmode = self.read_reg(®s::IfMode)?;
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ifmode.set_crc(mode);
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self.checksum_mode = mode;
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self.write_reg(®s::IfMode, &mut ifmode)?;
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Ok(())
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}
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pub fn set_sync_enable(&mut self, enable: bool) -> Result<(), SPI::Error> {
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self.update_reg(®s::GpioCon, |data| {
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data.set_sync_en(enable);
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})
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}
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pub fn setup_channel(
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&mut self, index: u8, in_pos: Input, in_neg: Input
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) -> Result<(), SPI::Error> {
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self.update_reg(®s::SetupCon { index }, |data| {
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data.set_bipolar(false);
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data.set_refbuf_pos(true);
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data.set_refbuf_neg(true);
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data.set_ainbuf_pos(true);
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data.set_ainbuf_neg(true);
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data.set_ref_sel(RefSource::External);
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})?;
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self.update_reg(®s::FiltCon { index }, |data| {
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data.set_enh_filt_en(true);
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data.set_enh_filt(PostFilter::F16SPS);
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data.set_order(DigitalFilterOrder::Sinc5Sinc1);
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// output data rate: 10 Hz
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data.set_odr(0b10011);
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})?;
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self.update_reg(®s::Channel { index }, |data| {
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data.set_setup(index);
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data.set_enabled(true);
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data.set_a_in_pos(in_pos);
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data.set_a_in_neg(in_neg);
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})?;
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Ok(())
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}
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pub fn get_calibration(&mut self, index: u8) -> Result<ChannelCalibration, SPI::Error> {
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let offset = self.read_reg(®s::Offset { index })?.offset();
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let gain = self.read_reg(®s::Gain { index })?.gain();
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let bipolar = self.read_reg(®s::SetupCon { index })?.bipolar();
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Ok(ChannelCalibration { offset, gain, bipolar })
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}
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pub fn start_continuous_conversion(&mut self) -> Result<(), SPI::Error> {
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let mut adc_mode = <regs::AdcMode as Register>::Data::empty();
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adc_mode.set_ref_en(true);
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adc_mode.set_mode(Mode::ContinuousConversion);
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self.write_reg(®s::AdcMode, &mut adc_mode)?;
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Ok(())
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}
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pub fn get_postfilter(&mut self, index: u8) -> Result<Option<PostFilter>, SPI::Error> {
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self.read_reg(®s::FiltCon { index })
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.map(|data| {
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if data.enh_filt_en() {
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Some(data.enh_filt())
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} else {
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None
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}
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})
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}
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pub fn set_postfilter(&mut self, index: u8, filter: Option<PostFilter>) -> Result<(), SPI::Error> {
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self.update_reg(®s::FiltCon { index }, |data| {
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match filter {
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None => data.set_enh_filt_en(false),
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Some(filter) => {
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data.set_enh_filt_en(true);
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data.set_enh_filt(filter);
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}
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}
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})
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}
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/// Returns the channel the data is from
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pub fn data_ready(&mut self) -> Result<Option<u8>, SPI::Error> {
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self.read_reg(®s::Status)
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.map(|status| {
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if status.ready() {
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Some(status.channel())
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} else {
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None
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}
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})
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}
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/// Get data
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pub fn read_data(&mut self) -> Result<u32, SPI::Error> {
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self.read_reg(®s::Data)
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.map(|data| data.data())
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}
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fn read_reg<R: regs::Register>(&mut self, reg: &R) -> Result<R::Data, SPI::Error> {
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let mut reg_data = R::Data::empty();
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let address = 0x40 | reg.address();
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let mut checksum = Checksum::new(self.checksum_mode);
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checksum.feed(&[address]);
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let checksum_out = checksum.result();
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loop {
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let checksum_in = self.transfer(address, reg_data.as_mut(), checksum_out)?;
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checksum.feed(®_data);
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let checksum_expected = checksum.result();
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if checksum_expected == checksum_in {
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break;
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}
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// Retry
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warn!("read_reg {:02X}: checksum error: {:?}!={:?}, retrying", reg.address(), checksum_expected, checksum_in);
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}
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Ok(reg_data)
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}
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fn write_reg<R: regs::Register>(&mut self, reg: &R, reg_data: &mut R::Data) -> Result<(), SPI::Error> {
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loop {
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let address = reg.address();
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let mut checksum = Checksum::new(match self.checksum_mode {
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ChecksumMode::Off => ChecksumMode::Off,
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// write checksums are always crc
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ChecksumMode::Xor => ChecksumMode::Crc,
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ChecksumMode::Crc => ChecksumMode::Crc,
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});
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checksum.feed(&[address]);
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checksum.feed(®_data);
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let checksum_out = checksum.result();
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let mut data = reg_data.clone();
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self.transfer(address, data.as_mut(), checksum_out)?;
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// Verification
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let readback_data = self.read_reg(reg)?;
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if *readback_data == **reg_data {
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return Ok(());
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}
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warn!("write_reg {:02X}: readback error, {:?}!={:?}, retrying", address, &*readback_data, &**reg_data);
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}
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}
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fn update_reg<R, F, A>(&mut self, reg: &R, f: F) -> Result<A, SPI::Error>
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where
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R: regs::Register,
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F: FnOnce(&mut R::Data) -> A,
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{
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let mut reg_data = self.read_reg(reg)?;
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let result = f(&mut reg_data);
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self.write_reg(reg, &mut reg_data)?;
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Ok(result)
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}
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pub fn reset(&mut self) -> Result<(), SPI::Error> {
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let mut buf = [0xFFu8; 8];
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let _ = self.nss.set_low();
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let result = self.spi.transfer(&mut buf);
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let _ = self.nss.set_high();
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result?;
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Ok(())
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}
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fn transfer<'w>(&mut self, addr: u8, reg_data: &'w mut [u8], checksum: Option<u8>) -> Result<Option<u8>, SPI::Error> {
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let mut addr_buf = [addr];
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let _ = self.nss.set_low();
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let result = match self.spi.transfer(&mut addr_buf) {
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Ok(_) => self.spi.transfer(reg_data),
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Err(e) => Err(e),
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};
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let result = match (result, checksum) {
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(Ok(_), None) =>
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Ok(None),
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(Ok(_), Some(checksum_out)) => {
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let mut checksum_buf = [checksum_out; 1];
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match self.spi.transfer(&mut checksum_buf) {
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Ok(_) => Ok(Some(checksum_buf[0])),
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Err(e) => Err(e),
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}
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}
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(Err(e), _) =>
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Err(e),
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};
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let _ = self.nss.set_high();
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result
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}
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}
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#[derive(Debug, Clone)]
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pub struct ChannelCalibration {
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offset: u32,
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gain: u32,
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bipolar: bool,
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}
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impl ChannelCalibration {
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pub fn convert_data(&self, data: u32) -> ElectricPotential {
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let data = if self.bipolar {
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(data as i32 - 0x80_0000) as f64
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} else {
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data as f64 / 2.0
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};
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let data = data / (self.gain as f64 / (0x40_0000 as f64));
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let data = data + (self.offset as i32 - 0x80_0000) as f64;
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let data = data / (2 << 23) as f64;
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const V_REF: f64 = 3.3;
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ElectricPotential::new::<volt>(data * V_REF / 0.75)
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}
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}
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@ -0,0 +1,60 @@
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#[derive(Clone, Copy, PartialEq)]
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#[repr(u8)]
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pub enum ChecksumMode {
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Off = 0b00,
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/// Seems much less reliable than `Crc`
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Xor = 0b01,
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Crc = 0b10,
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}
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impl From<u8> for ChecksumMode {
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fn from(x: u8) -> Self {
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match x {
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0 => ChecksumMode::Off,
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1 => ChecksumMode::Xor,
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_ => ChecksumMode::Crc,
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}
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}
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}
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pub struct Checksum {
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mode: ChecksumMode,
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state: u8,
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}
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impl Checksum {
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pub fn new(mode: ChecksumMode) -> Self {
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Checksum { mode, state: 0 }
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}
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fn feed_byte(&mut self, input: u8) {
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match self.mode {
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ChecksumMode::Off => {},
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ChecksumMode::Xor => self.state ^= input,
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ChecksumMode::Crc => {
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for i in 0..8 {
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let input_mask = 0x80 >> i;
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self.state = (self.state << 1) ^
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if ((self.state & 0x80) != 0) != ((input & input_mask) != 0) {
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0x07 /* x8 + x2 + x + 1 */
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} else {
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0
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};
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}
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}
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}
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}
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pub fn feed(&mut self, input: &[u8]) {
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for &b in input {
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self.feed_byte(b);
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}
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}
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pub fn result(&self) -> Option<u8> {
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match self.mode {
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ChecksumMode::Off => None,
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_ => Some(self.state)
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}
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}
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}
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@ -0,0 +1,221 @@
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use core::fmt;
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use num_traits::float::Float;
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use serde::{Serialize, Deserialize};
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use fugit::MegahertzU32;
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use stm32f4xx_hal::spi;
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pub mod regs;
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mod checksum;
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pub use checksum::ChecksumMode;
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mod adc;
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pub use adc::*;
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/// SPI Mode 3
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pub const SPI_MODE: spi::Mode = spi::Mode {
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polarity: spi::Polarity::IdleHigh,
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phase: spi::Phase::CaptureOnSecondTransition,
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};
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/// 2 MHz
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pub const SPI_CLOCK_MHZ: MegahertzU32 = MegahertzU32::from_raw(2);
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pub const MAX_VALUE: u32 = 0xFF_FFFF;
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#[derive(Clone, Copy, Debug)]
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#[repr(u8)]
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pub enum Mode {
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ContinuousConversion = 0b000,
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SingleConversion = 0b001,
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Standby = 0b010,
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PowerDown = 0b011,
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InternalOffsetCalibration = 0b100,
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Invalid,
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SystemOffsetCalibration = 0b110,
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SystemGainCalibration = 0b111,
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}
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impl From<u8> for Mode {
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fn from(x: u8) -> Self {
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use Mode::*;
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match x {
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0b000 => ContinuousConversion,
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0b001 => SingleConversion,
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0b010 => Standby,
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0b011 => PowerDown,
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0b100 => InternalOffsetCalibration,
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0b110 => SystemOffsetCalibration,
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0b111 => SystemGainCalibration,
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_ => Invalid,
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}
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}
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}
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#[derive(Clone, Copy, Debug)]
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#[repr(u8)]
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pub enum Input {
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Ain0 = 0,
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Ain1 = 1,
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Ain2 = 2,
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Ain3 = 3,
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Ain4 = 4,
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TemperaturePos = 17,
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TemperatureNeg = 18,
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AnalogSupplyPos = 19,
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AnalogSupplyNeg = 20,
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RefPos = 21,
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RefNeg = 22,
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Invalid = 0b11111,
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}
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impl From<u8> for Input {
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fn from(x: u8) -> Self {
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match x {
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0 => Input::Ain0,
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1 => Input::Ain1,
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2 => Input::Ain2,
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3 => Input::Ain3,
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4 => Input::Ain4,
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17 => Input::TemperaturePos,
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18 => Input::TemperatureNeg,
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19 => Input::AnalogSupplyPos,
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20 => Input::AnalogSupplyNeg,
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21 => Input::RefPos,
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22 => Input::RefNeg,
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_ => Input::Invalid,
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}
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}
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}
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impl fmt::Display for Input {
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fn fmt(&self, fmt: &mut fmt::Formatter) -> Result<(), fmt::Error> {
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use Input::*;
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match self {
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Ain0 => "ain0",
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Ain1 => "ain1",
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Ain2 => "ain2",
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Ain3 => "ain3",
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Ain4 => "ain4",
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TemperaturePos => "temperature+",
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TemperatureNeg => "temperature-",
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AnalogSupplyPos => "analogsupply+",
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AnalogSupplyNeg => "analogsupply-",
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RefPos => "ref+",
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RefNeg => "ref-",
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_ => "<INVALID>",
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}.fmt(fmt)
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}
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}
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/// Reference source for ADC conversion
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#[repr(u8)]
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pub enum RefSource {
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/// External reference
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External = 0b00,
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/// Internal 2.5V reference
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Internal = 0b10,
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/// AVDD1 − AVSS
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Avdd1MinusAvss = 0b11,
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Invalid = 0b01,
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}
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impl From<u8> for RefSource {
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fn from(x: u8) -> Self {
|
||||
match x {
|
||||
0 => RefSource::External,
|
||||
1 => RefSource::Internal,
|
||||
2 => RefSource::Avdd1MinusAvss,
|
||||
_ => RefSource::Invalid,
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl fmt::Display for RefSource {
|
||||
fn fmt(&self, fmt: &mut fmt::Formatter) -> Result<(), fmt::Error> {
|
||||
use RefSource::*;
|
||||
|
||||
match self {
|
||||
External => "external",
|
||||
Internal => "internal",
|
||||
Avdd1MinusAvss => "avdd1-avss",
|
||||
_ => "<INVALID>",
|
||||
}.fmt(fmt)
|
||||
}
|
||||
}
|
||||
|
||||
#[derive(Clone, Copy, Debug, PartialEq, Serialize, Deserialize)]
|
||||
#[repr(u8)]
|
||||
pub enum PostFilter {
|
||||
/// 27 SPS, 47 dB rejection, 36.7 ms settling
|
||||
F27SPS = 0b010,
|
||||
/// 21.25 SPS, 62 dB rejection, 40 ms settling
|
||||
F21SPS = 0b011,
|
||||
/// 20 SPS, 86 dB rejection, 50 ms settling
|
||||
F20SPS = 0b101,
|
||||
/// 16.67 SPS, 92 dB rejection, 60 ms settling
|
||||
F16SPS = 0b110,
|
||||
Invalid = 0b111,
|
||||
}
|
||||
|
||||
impl PostFilter {
|
||||
pub const VALID_VALUES: &'static [Self] = &[
|
||||
PostFilter::F27SPS,
|
||||
PostFilter::F21SPS,
|
||||
PostFilter::F20SPS,
|
||||
PostFilter::F16SPS,
|
||||
];
|
||||
|
||||
pub fn closest(rate: f32) -> Option<Self> {
|
||||
let mut best: Option<(f32, Self)> = None;
|
||||
for value in Self::VALID_VALUES {
|
||||
let error = (rate - value.output_rate().unwrap()).abs();
|
||||
let better = best
|
||||
.map(|(best_error, _)| error < best_error)
|
||||
.unwrap_or(true);
|
||||
if better {
|
||||
best = Some((error, *value));
|
||||
}
|
||||
}
|
||||
best.map(|(_, best)| best)
|
||||
}
|
||||
|
||||
/// Samples per Second
|
||||
pub fn output_rate(&self) -> Option<f32> {
|
||||
match self {
|
||||
PostFilter::F27SPS => Some(27.0),
|
||||
PostFilter::F21SPS => Some(21.25),
|
||||
PostFilter::F20SPS => Some(20.0),
|
||||
PostFilter::F16SPS => Some(16.67),
|
||||
PostFilter::Invalid => None,
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl From<u8> for PostFilter {
|
||||
fn from(x: u8) -> Self {
|
||||
match x {
|
||||
0b010 => PostFilter::F27SPS,
|
||||
0b011 => PostFilter::F21SPS,
|
||||
0b101 => PostFilter::F20SPS,
|
||||
0b110 => PostFilter::F16SPS,
|
||||
_ => PostFilter::Invalid,
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#[repr(u8)]
|
||||
pub enum DigitalFilterOrder {
|
||||
Sinc5Sinc1 = 0b00,
|
||||
Sinc3 = 0b11,
|
||||
Invalid = 0b10,
|
||||
}
|
||||
|
||||
impl From<u8> for DigitalFilterOrder {
|
||||
fn from(x: u8) -> Self {
|
||||
match x {
|
||||
0b00 => DigitalFilterOrder::Sinc5Sinc1,
|
||||
0b11 => DigitalFilterOrder::Sinc3,
|
||||
_ => DigitalFilterOrder::Invalid,
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,267 @@
|
|||
use core::ops::{Deref, DerefMut};
|
||||
use byteorder::{BigEndian, ByteOrder};
|
||||
use bit_field::BitField;
|
||||
|
||||
use super::*;
|
||||
|
||||
pub trait Register {
|
||||
type Data: RegisterData;
|
||||
fn address(&self) -> u8;
|
||||
}
|
||||
|
||||
pub trait RegisterData: Clone + Deref<Target=[u8]> + DerefMut {
|
||||
fn empty() -> Self;
|
||||
}
|
||||
|
||||
macro_rules! def_reg {
|
||||
($Reg: ident, $reg: ident, $addr: expr, $size: expr) => {
|
||||
/// AD7172 register
|
||||
pub struct $Reg;
|
||||
impl Register for $Reg {
|
||||
/// Register contents
|
||||
type Data = $reg::Data;
|
||||
/// Register address
|
||||
fn address(&self) -> u8 {
|
||||
$addr
|
||||
}
|
||||
}
|
||||
mod $reg {
|
||||
/// Register contents
|
||||
#[derive(Clone)]
|
||||
pub struct Data(pub [u8; $size]);
|
||||
impl super::RegisterData for Data {
|
||||
/// Generate zeroed register contents
|
||||
fn empty() -> Self {
|
||||
Data([0; $size])
|
||||
}
|
||||
}
|
||||
impl core::ops::Deref for Data {
|
||||
type Target = [u8];
|
||||
fn deref(&self) -> &[u8] {
|
||||
&self.0
|
||||
}
|
||||
}
|
||||
impl core::ops::DerefMut for Data {
|
||||
fn deref_mut(&mut self) -> &mut [u8] {
|
||||
&mut self.0
|
||||
}
|
||||
}
|
||||
}
|
||||
};
|
||||
($Reg: ident, u8, $reg: ident, $addr: expr, $size: expr) => {
|
||||
pub struct $Reg { pub index: u8, }
|
||||
impl Register for $Reg {
|
||||
type Data = $reg::Data;
|
||||
fn address(&self) -> u8 {
|
||||
$addr + self.index
|
||||
}
|
||||
}
|
||||
mod $reg {
|
||||
#[derive(Clone)]
|
||||
pub struct Data(pub [u8; $size]);
|
||||
impl super::RegisterData for Data {
|
||||
fn empty() -> Self {
|
||||
Data([0; $size])
|
||||
}
|
||||
}
|
||||
impl core::ops::Deref for Data {
|
||||
type Target = [u8];
|
||||
fn deref(&self) -> &[u8] {
|
||||
&self.0
|
||||
}
|
||||
}
|
||||
impl core::ops::DerefMut for Data {
|
||||
fn deref_mut(&mut self) -> &mut [u8] {
|
||||
&mut self.0
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
macro_rules! reg_bit {
|
||||
($getter: ident, $byte: expr, $bit: expr, $doc: expr) => {
|
||||
#[allow(unused)]
|
||||
#[doc = $doc]
|
||||
pub fn $getter(&self) -> bool {
|
||||
self.0[$byte].get_bit($bit)
|
||||
}
|
||||
};
|
||||
($getter: ident, $setter: ident, $byte: expr, $bit: expr, $doc: expr) => {
|
||||
#[allow(unused)]
|
||||
#[doc = $doc]
|
||||
pub fn $getter(&self) -> bool {
|
||||
self.0[$byte].get_bit($bit)
|
||||
}
|
||||
#[allow(unused)]
|
||||
#[doc = $doc]
|
||||
pub fn $setter(&mut self, value: bool) {
|
||||
self.0[$byte].set_bit($bit, value);
|
||||
}
|
||||
};
|
||||
}
|
||||
|
||||
macro_rules! reg_bits {
|
||||
($getter: ident, $byte: expr, $bits: expr, $doc: expr) => {
|
||||
#[allow(unused)]
|
||||
#[doc = $doc]
|
||||
pub fn $getter(&self) -> u8 {
|
||||
self.0[$byte].get_bits($bits)
|
||||
}
|
||||
};
|
||||
($getter: ident, $setter: ident, $byte: expr, $bits: expr, $doc: expr) => {
|
||||
#[allow(unused)]
|
||||
#[doc = $doc]
|
||||
pub fn $getter(&self) -> u8 {
|
||||
self.0[$byte].get_bits($bits)
|
||||
}
|
||||
#[allow(unused)]
|
||||
#[doc = $doc]
|
||||
pub fn $setter(&mut self, value: u8) {
|
||||
self.0[$byte].set_bits($bits, value);
|
||||
}
|
||||
};
|
||||
($getter: ident, $byte: expr, $bits: expr, $ty: ty, $doc: expr) => {
|
||||
#[allow(unused)]
|
||||
#[doc = $doc]
|
||||
pub fn $getter(&self) -> $ty {
|
||||
self.0[$byte].get_bits($bits) as $ty
|
||||
}
|
||||
};
|
||||
($getter: ident, $setter: ident, $byte: expr, $bits: expr, $ty: ty, $doc: expr) => {
|
||||
#[allow(unused)]
|
||||
#[doc = $doc]
|
||||
pub fn $getter(&self) -> $ty {
|
||||
self.0[$byte].get_bits($bits).into()
|
||||
}
|
||||
#[allow(unused)]
|
||||
#[doc = $doc]
|
||||
pub fn $setter(&mut self, value: $ty) {
|
||||
self.0[$byte].set_bits($bits, value as u8);
|
||||
}
|
||||
};
|
||||
}
|
||||
|
||||
def_reg!(Status, status, 0x00, 1);
|
||||
impl status::Data {
|
||||
/// Is there new data to read?
|
||||
pub fn ready(&self) -> bool {
|
||||
! self.not_ready()
|
||||
}
|
||||
|
||||
reg_bit!(not_ready, 0, 7, "No data ready indicator");
|
||||
reg_bits!(channel, 0, 0..=1, "Channel for which data is ready");
|
||||
reg_bit!(adc_error, 0, 6, "ADC error");
|
||||
reg_bit!(crc_error, 0, 5, "SPI CRC error");
|
||||
reg_bit!(reg_error, 0, 4, "Register error");
|
||||
}
|
||||
|
||||
def_reg!(AdcMode, adc_mode, 0x01, 2);
|
||||
impl adc_mode::Data {
|
||||
reg_bits!(delay, set_delay, 0, 0..=2, "Delay after channel switch");
|
||||
reg_bit!(sing_cyc, set_sing_cyc, 0, 5, "Can only used with single channel");
|
||||
reg_bit!(hide_delay, set_hide_delay, 0, 6, "Hide delay");
|
||||
reg_bit!(ref_en, set_ref_en, 0, 7, "Enable internal reference, output buffered 2.5 V to REFOUT");
|
||||
reg_bits!(clockset, set_clocksel, 1, 2..=3, "Clock source");
|
||||
reg_bits!(mode, set_mode, 1, 4..=6, Mode, "Operating mode");
|
||||
}
|
||||
|
||||
def_reg!(IfMode, if_mode, 0x02, 2);
|
||||
impl if_mode::Data {
|
||||
reg_bits!(crc, set_crc, 1, 2..=3, ChecksumMode, "SPI checksum mode");
|
||||
}
|
||||
|
||||
def_reg!(Data, data, 0x04, 3);
|
||||
impl data::Data {
|
||||
pub fn data(&self) -> u32 {
|
||||
(u32::from(self.0[0]) << 16) |
|
||||
(u32::from(self.0[1]) << 8) |
|
||||
u32::from(self.0[2])
|
||||
}
|
||||
}
|
||||
|
||||
def_reg!(GpioCon, gpio_con, 0x06, 2);
|
||||
impl gpio_con::Data {
|
||||
reg_bit!(sync_en, set_sync_en, 0, 3, "Enables the SYNC/ERROR pin as a sync input");
|
||||
}
|
||||
|
||||
def_reg!(Id, id, 0x07, 2);
|
||||
impl id::Data {
|
||||
pub fn id(&self) -> u16 {
|
||||
BigEndian::read_u16(&self.0)
|
||||
}
|
||||
}
|
||||
|
||||
def_reg!(Channel, u8, channel, 0x10, 2);
|
||||
impl channel::Data {
|
||||
reg_bit!(enabled, set_enabled, 0, 7, "Channel enabled");
|
||||
reg_bits!(setup, set_setup, 0, 4..=5, "Setup number");
|
||||
|
||||
/// Which input is connected to positive input of this channel
|
||||
#[allow(unused)]
|
||||
pub fn a_in_pos(&self) -> Input {
|
||||
((self.0[0].get_bits(0..=1) << 3) |
|
||||
self.0[1].get_bits(5..=7)).into()
|
||||
}
|
||||
/// Set which input is connected to positive input of this channel
|
||||
#[allow(unused)]
|
||||
pub fn set_a_in_pos(&mut self, value: Input) {
|
||||
let value = value as u8;
|
||||
self.0[0].set_bits(0..=1, value >> 3);
|
||||
self.0[1].set_bits(5..=7, value & 0x7);
|
||||
}
|
||||
reg_bits!(a_in_neg, set_a_in_neg, 1, 0..=4, Input,
|
||||
"Which input is connected to negative input of this channel");
|
||||
}
|
||||
|
||||
def_reg!(SetupCon, u8, setup_con, 0x20, 2);
|
||||
impl setup_con::Data {
|
||||
reg_bit!(bipolar, set_bipolar, 0, 4, "Unipolar (`false`) or bipolar (`true`) coded output");
|
||||
reg_bit!(refbuf_pos, set_refbuf_pos, 0, 3, "Enable REF+ input buffer");
|
||||
reg_bit!(refbuf_neg, set_refbuf_neg, 0, 2, "Enable REF- input buffer");
|
||||
reg_bit!(ainbuf_pos, set_ainbuf_pos, 0, 1, "Enable AIN+ input buffer");
|
||||
reg_bit!(ainbuf_neg, set_ainbuf_neg, 0, 0, "Enable AIN- input buffer");
|
||||
reg_bit!(burnout_en, 1, 7, "enables a 10 µA current source on the positive analog input selected and a 10 µA current sink on the negative analog input selected");
|
||||
reg_bits!(ref_sel, set_ref_sel, 1, 4..=5, RefSource, "Select reference source for conversion");
|
||||
}
|
||||
|
||||
def_reg!(FiltCon, u8, filt_con, 0x28, 2);
|
||||
impl filt_con::Data {
|
||||
reg_bit!(sinc3_map, 0, 7, "If set, mapping of filter register changes to directly program the decimation rate of the sinc3 filter");
|
||||
reg_bit!(enh_filt_en, set_enh_filt_en, 0, 3, "Enable postfilters for enhanced 50Hz and 60Hz rejection");
|
||||
reg_bits!(enh_filt, set_enh_filt, 0, 0..=2, PostFilter, "Select postfilters for enhanced 50Hz and 60Hz rejection");
|
||||
reg_bits!(order, set_order, 1, 5..=6, DigitalFilterOrder, "order of the digital filter that processes the modulator data");
|
||||
reg_bits!(odr, set_odr, 1, 0..=4, "Output data rate");
|
||||
}
|
||||
|
||||
def_reg!(Offset, u8, offset, 0x30, 3);
|
||||
impl offset::Data {
|
||||
#[allow(unused)]
|
||||
pub fn offset(&self) -> u32 {
|
||||
(u32::from(self.0[0]) << 16) |
|
||||
(u32::from(self.0[1]) << 8) |
|
||||
u32::from(self.0[2])
|
||||
}
|
||||
#[allow(unused)]
|
||||
pub fn set_offset(&mut self, value: u32) {
|
||||
self.0[0] = (value >> 16) as u8;
|
||||
self.0[1] = (value >> 8) as u8;
|
||||
self.0[2] = value as u8;
|
||||
}
|
||||
}
|
||||
|
||||
def_reg!(Gain, u8, gain, 0x38, 3);
|
||||
impl gain::Data {
|
||||
#[allow(unused)]
|
||||
pub fn gain(&self) -> u32 {
|
||||
(u32::from(self.0[0]) << 16) |
|
||||
(u32::from(self.0[1]) << 8) |
|
||||
u32::from(self.0[2])
|
||||
}
|
||||
#[allow(unused)]
|
||||
pub fn set_gain(&mut self, value: u32) {
|
||||
self.0[0] = (value >> 16) as u8;
|
||||
self.0[1] = (value >> 8) as u8;
|
||||
self.0[2] = value as u8;
|
||||
}
|
||||
}
|
||||
|
|
@ -1,3 +1,4 @@
|
|||
pub mod ad5680;
|
||||
pub mod max1968;
|
||||
pub mod thermostat;
|
||||
pub mod thermostat;
|
||||
pub mod ad7172;
|
||||
Loading…
Reference in New Issue