272 lines
9.4 KiB
Rust
272 lines
9.4 KiB
Rust
use cortex_m;
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use tm4c129x;
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mod gpio;
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const LED1: u8 = 0x10; // PK4
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const LED2: u8 = 0x40; // PK6
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const FD_ADC: u8 = 0x01; // PE0
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const FV_ADC: u8 = 0x02; // PE1
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const FBI_ADC: u8 = 0x04; // PE2
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const IC_ADC: u8 = 0x08; // PE3
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const FBV_ADC: u8 = 0x20; // PD5
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const AV_ADC: u8 = 0x40; // PD6
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const FV_ERRN: u8 = 0x01; // PL0
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const FBV_ERRN: u8 = 0x02; // PL1
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const FBI_ERRN: u8 = 0x04; // PL2
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const AV_ERRN: u8 = 0x08; // PL3
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const AI_ERRN: u8 = 0x10; // PL4
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const ERR_LATCHN: u8 = 0x20; // PL5
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const BTNN: u8 = 0x80; // PL7
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const ERR_RESN: u8 = 0x01; // PQ0
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pub const PWM_LOAD: u16 = (/*pwmclk*/120_000_000u32 / /*freq*/100_000) as u16;
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const UART_DIV: u32 = (((/*sysclk*/120_000_000 * 8) / /*baud*/115200) + 1) / 2;
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pub const AV_ADC_GAIN: f32 = 6.792703150912105;
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pub const FV_ADC_GAIN: f32 = 501.83449105726623;
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pub const FBI_ADC_GAIN: f32 = 1333.3333333333333;
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pub const FBI_ADC_OFFSET: f32 = 96.0;
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pub const FD_ADC_GAIN: f32 = 3111.1111111111104;
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pub const FD_ADC_OFFSET: f32 = 96.0;
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pub const FBV_ADC_GAIN: f32 = 49.13796058269066;
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pub const FBV_PWM_GAIN: f32 = 0.07641071428571428;
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pub const IC_ADC_GAIN_LOW: f32 = 1333333333333.3333;
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pub const IC_ADC_GAIN_MED: f32 = 13201320132.0132;
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pub const IC_ADC_GAIN_HIGH: f32 = 133320001.3332;
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pub const IC_ADC_OFFSET: f32 = 96.0;
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pub const FBI_R223: f32 = 200.0;
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pub const FBI_R224: f32 = 39.0;
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pub const FBI_R225: f32 = 22000.0;
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pub fn reset_error() {
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cortex_m::interrupt::free(|_cs| {
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let gpio_q = unsafe { &*tm4c129x::GPIO_PORTQ::ptr() };
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gpio_q.data.modify(|r, w| w.data().bits(r.data().bits() & !ERR_RESN));
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gpio_q.data.modify(|r, w| w.data().bits(r.data().bits() | ERR_RESN));
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});
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}
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pub fn error_latched() -> bool {
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cortex_m::interrupt::free(|_cs| {
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let gpio_l = unsafe { &*tm4c129x::GPIO_PORTL::ptr() };
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gpio_l.data.read().bits() as u8 & ERR_LATCHN == 0
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})
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}
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pub fn process_errors() {
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let gpio_dat = cortex_m::interrupt::free(|_cs| {
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let gpio_l = unsafe { &*tm4c129x::GPIO_PORTL::ptr() };
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gpio_l.data.read().bits() as u8
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});
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if gpio_dat & FV_ERRN == 0 {
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println!("Filament overvolt");
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}
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if gpio_dat & FBV_ERRN == 0 {
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println!("Filament bias overvolt");
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}
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if gpio_dat & FBI_ERRN == 0 {
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println!("Filament bias overcurrent");
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}
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if gpio_dat & AV_ERRN == 0 {
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println!("Anode overvolt");
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}
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if gpio_dat & AI_ERRN == 0 {
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println!("Anode overcurrent");
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}
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}
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pub fn init() {
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cortex_m::interrupt::free(|_cs| {
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let sysctl = unsafe { &*tm4c129x::SYSCTL::ptr() };
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// Set up main oscillator
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sysctl.moscctl.write(|w| w.noxtal().bit(false));
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sysctl.moscctl.modify(|_, w| w.pwrdn().bit(false).oscrng().bit(true));
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// Prepare flash for the high-freq clk
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sysctl.memtim0.write(|w| unsafe { w.bits(0x01950195u32) });
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sysctl.rsclkcfg.write(|w| unsafe { w.bits(0x80000000u32) });
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// Set up PLL with fVCO=480 MHz
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sysctl.pllfreq1.write(|w| w.q().bits(0).n().bits(4));
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sysctl.pllfreq0.write(|w| w.mint().bits(96).pllpwr().bit(true));
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sysctl.rsclkcfg.modify(|_, w| w.pllsrc().mosc().newfreq().bit(true));
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while !sysctl.pllstat.read().lock().bit() {}
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// Switch to PLL (sysclk=120MHz)
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sysctl.rsclkcfg.write(|w| unsafe { w.bits(0b1_0_0_1_0011_0000_0000000000_0000000011) });
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// Bring up GPIO ports A, D, E, F, G, K, L, M, P, Q
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sysctl.rcgcgpio.modify(|_, w| {
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w.r0().bit(true)
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.r3().bit(true)
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.r4().bit(true)
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.r5().bit(true)
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.r6().bit(true)
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.r9().bit(true)
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.r10().bit(true)
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.r11().bit(true)
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.r13().bit(true)
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.r14().bit(true)
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});
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while !sysctl.prgpio.read().r0().bit() {}
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while !sysctl.prgpio.read().r3().bit() {}
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while !sysctl.prgpio.read().r4().bit() {}
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while !sysctl.prgpio.read().r5().bit() {}
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while !sysctl.prgpio.read().r6().bit() {}
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while !sysctl.prgpio.read().r9().bit() {}
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while !sysctl.prgpio.read().r10().bit() {}
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while !sysctl.prgpio.read().r11().bit() {}
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while !sysctl.prgpio.read().r13().bit() {}
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while !sysctl.prgpio.read().r14().bit() {}
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// Set up UART0
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let gpio_a = unsafe { &*tm4c129x::GPIO_PORTA_AHB::ptr() };
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gpio_a.dir.write(|w| w.dir().bits(0b11));
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gpio_a.den.write(|w| w.den().bits(0b11));
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gpio_a.afsel.write(|w| w.afsel().bits(0b11));
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gpio_a.pctl.write(|w| unsafe { w.pmc0().bits(1).pmc1().bits(1) });
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sysctl.rcgcuart.modify(|_, w| w.r0().bit(true));
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while !sysctl.pruart.read().r0().bit() {}
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let uart_0 = unsafe { &*tm4c129x::UART0::ptr() };
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uart_0.cc.write(|w| w.cs().sysclk());
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uart_0.ibrd.write(|w| w.divint().bits((UART_DIV / 64) as u16));
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uart_0.fbrd.write(|w| w.divfrac().bits((UART_DIV % 64) as u8));
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uart_0.lcrh.write(|w| w.wlen()._8().fen().bit(true));
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uart_0.ctl.write(|w| w.rxe().bit(true).txe().bit(true).uarten().bit(true));
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// Set up PWMs
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let gpio_m = unsafe { &*tm4c129x::GPIO_PORTM::ptr() };
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// Output
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gpio_m.dir.write(|w| w.dir().bits(0xff));
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// Enable
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gpio_m.den.write(|w| w.den().bits(0xff));
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// Alternate function
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gpio_m.afsel.write(|w| w.afsel().bits(0xff));
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// Function: Timer PWM
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gpio_m.pctl.write(|w| unsafe {
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w
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// t2ccp0
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.pmc0().bits(3)
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// t2ccp1
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.pmc1().bits(3)
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// t3ccp0
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.pmc2().bits(3)
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// t3ccp1
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.pmc3().bits(3)
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// t4ccp0
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.pmc4().bits(3)
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// t4ccp1
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.pmc5().bits(3)
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// t5ccp0
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.pmc6().bits(3)
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// t5ccp1
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.pmc7().bits(3)
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});
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// Manual: 13.4.5 PWM Mode
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macro_rules! setup_timer_pwm {
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($T: tt) => (
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let timer = unsafe { &*tm4c129x::$T::ptr() };
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timer.cfg.write(|w| unsafe { w.bits(4) });
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timer.tamr.modify(|_, w| unsafe {
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w
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.taams().bit(true)
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.tacmr().bit(false)
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.tamr().bits(2)
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});
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timer.tbmr.modify(|_, w| unsafe {
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w
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.tbams().bit(true)
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.tbcmr().bit(false)
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.tbmr().bits(2)
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});
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timer.ctl.modify(|_, w| {
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w
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.tapwml().bit(false)
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.tbpwml().bit(false)
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});
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// no prescaler
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// no interrupts
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timer.tailr.write(|w| unsafe { w.bits(0xFFFF) });
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timer.tbilr.write(|w| unsafe { w.bits(0xFFFF) });
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timer.tamatchr.write(|w| unsafe { w.bits(0x8000) });
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timer.tbmatchr.write(|w| unsafe { w.bits(0x8000) });
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timer.ctl.modify(|_, w| {
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w
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.taen().bit(true)
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.tben().bit(true)
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});
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)
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}
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setup_timer_pwm!(TIMER2);
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setup_timer_pwm!(TIMER3);
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setup_timer_pwm!(TIMER4);
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setup_timer_pwm!(TIMER5);
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});
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}
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pub fn start_adc() {
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cortex_m::interrupt::free(|_cs| {
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let sysctl = unsafe { &*tm4c129x::SYSCTL::ptr() };
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let gpio_d = unsafe { &*tm4c129x::GPIO_PORTD_AHB::ptr() };
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let gpio_e = unsafe { &*tm4c129x::GPIO_PORTE_AHB::ptr() };
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gpio_d.afsel.write(|w| w.afsel().bits(FBV_ADC|AV_ADC));
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gpio_d.amsel.write(|w| w.amsel().bits(FBV_ADC|AV_ADC));
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gpio_e.afsel.write(|w| w.afsel().bits(FD_ADC|FV_ADC|FBI_ADC|IC_ADC));
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gpio_e.amsel.write(|w| w.amsel().bits(FD_ADC|FV_ADC|FBI_ADC|IC_ADC));
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sysctl.rcgcadc.modify(|_, w| w.r0().bit(true));
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while !sysctl.pradc.read().r0().bit() {}
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let adc0 = unsafe { &*tm4c129x::ADC0::ptr() };
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// VCO 480 / 15 = 32MHz ADC clock
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adc0.cc.write(|w| w.cs().syspll().clkdiv().bits(15-1));
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adc0.im.write(|w| w.mask0().bit(true));
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adc0.emux.write(|w| w.em0().always());
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adc0.ssmux0.write(|w| {
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w.mux0().bits(0) // IC_ADC
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.mux1().bits(1) // FBI_ADC
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.mux2().bits(2) // FV_ADC
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.mux3().bits(3) // FD_ADC
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.mux4().bits(5) // AV_ADC
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.mux5().bits(6) // FBV_ADC
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});
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adc0.ssctl0.write(|w| w.ie5().bit(true).end5().bit(true));
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adc0.sstsh0.write(|w| {
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w.tsh0()._4()
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.tsh1()._4()
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.tsh2()._4()
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.tsh3()._4()
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.tsh4()._4()
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.tsh5()._4()
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});
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adc0.sac.write(|w| w.avg()._64x());
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adc0.ctl.write(|w| w.vref().bit(true));
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adc0.actss.write(|w| w.asen0().bit(true));
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let mut cp = unsafe { tm4c129x::CorePeripherals::steal() };
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cp.NVIC.enable(tm4c129x::Interrupt::ADC0SS0);
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});
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}
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pub fn get_mac_address() -> [u8; 6] {
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let (userreg0, userreg1) = cortex_m::interrupt::free(|_cs| {
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let flashctl = unsafe { &*tm4c129x::FLASH_CTRL::ptr() };
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(flashctl.userreg0.read().bits(),
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flashctl.userreg1.read().bits())
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});
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[userreg0 as u8, (userreg0 >> 8) as u8, (userreg0 >> 16) as u8,
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userreg1 as u8, (userreg1 >> 8) as u8, (userreg1 >> 16) as u8]
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}
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