133 lines
3.2 KiB
Rust
133 lines
3.2 KiB
Rust
#![no_main]
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#![no_std]
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use panic_semihosting as _;
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use stm32h7xx_hal::hal::digital::v2::{
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InputPin,
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OutputPin,
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};
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use stm32h7xx_hal::{pac, prelude::*, spi};
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use cortex_m;
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use cortex_m::asm::nop;
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use cortex_m_rt::entry;
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use cortex_m_semihosting::hprintln;
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use core::ptr;
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use nb::block;
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#[entry]
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fn main() -> ! {
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hprintln!("Flashing configuration bitstream to iCE40 HX8K on Humpback.").unwrap();
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let cp = cortex_m::Peripherals::take().unwrap();
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let dp = pac::Peripherals::take().unwrap();
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let pwr = dp.PWR.constrain();
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let vos = pwr.freeze();
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let rcc = dp.RCC.constrain();
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let ccdr = rcc
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.sys_ck(400.mhz())
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.pll1_q_ck(48.mhz())
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.freeze(vos, &dp.SYSCFG);
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let mut delay = cp.SYST.delay(ccdr.clocks);
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let gpioa = dp.GPIOA.split(ccdr.peripheral.GPIOA);
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let gpiob = dp.GPIOB.split(ccdr.peripheral.GPIOB);
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let gpiod = dp.GPIOD.split(ccdr.peripheral.GPIOD);
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let gpiof = dp.GPIOF.split(ccdr.peripheral.GPIOF);
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// Using SPI_1 alternate functions (af5)
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let fpga_sck = gpiob.pb3.into_alternate_af5();
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let fpga_sdo = gpiob.pb4.into_alternate_af5();
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let fpga_sdi = gpiob.pb5.into_alternate_af5();
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// Setup SPI_SS_B and CRESET_B
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let mut fpga_ss = gpioa.pa4.into_push_pull_output();
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let mut fpga_creset = gpiof.pf3.into_open_drain_output();
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// Setup CDONE
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let fpga_cdone = gpiod.pd15.into_pull_up_input();
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// Setup SPI interface
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let mut fpga_cfg_spi = dp.SPI1.spi(
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(fpga_sck, fpga_sdo, fpga_sdi),
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spi::MODE_3,
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12.mhz(),
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ccdr.peripheral.SPI1,
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&ccdr.clocks,
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);
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// Data buffer setup
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let mut dummy_byte :[u8; 1] = [0x00];
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let mut dummy_13_bytes :[u8; 13] = [0x00; 13];
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// Drive CRESET_B low
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fpga_creset.set_low().unwrap();
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// Drive SPI_SS_B low
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fpga_ss.set_low().unwrap();
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// Wait at least 200ns
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delay.delay_us(1_u16);
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// Drive CRESET_B high
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fpga_creset.set_high().unwrap();
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// Wait at least another 1200us to clear internal config memory
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delay.delay_us(1200_u16);
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// Before data transmission starts, check if C_DONE is truly dine
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match fpga_cdone.is_high() {
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Ok(false) => hprintln!("Reset successful!"),
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Ok(_) => hprintln!("Reset unsuccessful!"),
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Err(_) => hprintln!("Reset error!"),
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}.unwrap();
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// Set SPI_SS_B high
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fpga_ss.set_high().unwrap();
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// Send 8 dummy clock, effectively 1 byte of 0x00
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fpga_cfg_spi.transfer(&mut dummy_byte).unwrap();
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// Drive SPI_SS_B low
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fpga_ss.set_low().unwrap();
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// Send the whole image without interruption
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let base_address = 0x08100000;
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let size = 135100;
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for index in 0..size {
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unsafe {
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let data :u8 = ptr::read_volatile((base_address + index) as *const u8);
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block!(fpga_cfg_spi.send(data)).unwrap();
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block!(fpga_cfg_spi.read()).unwrap();
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}
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}
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// Drive SPI_SS_B high
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fpga_ss.set_high().unwrap();
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// Send at another 100 dummy clocks (choosing 13 bytes)
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fpga_cfg_spi.transfer(&mut dummy_13_bytes).unwrap();
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// Check the CDONE output from FPGA
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if !(fpga_cdone.is_high().unwrap()) {
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hprintln!("ERROR!").unwrap();
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}
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else {
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hprintln!("Configuration successful!").unwrap();
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// Send at least another 49 clock cycles to activate IO pins (choosing same 13 bytes)
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fpga_cfg_spi.transfer(&mut dummy_13_bytes).unwrap();
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hprintln!("User I/O pins activated.").unwrap();
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}
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loop {
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nop();
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}
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}
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