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2 Commits
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8f4a97c97e
Author | SHA1 | Date |
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occheung | 8f4a97c97e | |
occheung | 0543e98956 |
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@ -1,5 +1,5 @@
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[target.thumbv7em-none-eabihf]
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[target.thumbv7em-none-eabihf]
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runner = "gdb -q -x gdb_config/fpga_config.gdb"
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runner = "gdb -q -x gdb_config/debug.gdb"
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rustflags = [
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rustflags = [
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"-C", "link-arg=-Tlink.x",
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"-C", "link-arg=-Tlink.x",
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]
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]
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@ -1,4 +1,5 @@
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use embedded_hal::blocking::spi::Transfer;
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use embedded_hal::blocking::spi::Transfer;
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use cortex_m_semihosting::hprintln;
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use crate::Error;
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use crate::Error;
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/*
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/*
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@ -6,6 +7,7 @@ use crate::Error;
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*/
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*/
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macro_rules! construct_bitmask {
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macro_rules! construct_bitmask {
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($collection: ident; $($name: ident, $shift: expr, $width: expr),+) => {
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($collection: ident; $($name: ident, $shift: expr, $width: expr),+) => {
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#[derive(Debug, Copy, Clone)]
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pub enum $collection {
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pub enum $collection {
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$(
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$(
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$name,
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$name,
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@ -33,7 +35,7 @@ macro_rules! construct_bitmask {
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$collection::$name => {
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$collection::$name => {
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let mut mask: u32 = 0;
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let mut mask: u32 = 0;
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for bit in 0..$width {
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for bit in 0..$width {
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mask != 1 << ($width + bit);
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mask |= (1 << ($shift + bit));
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}
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}
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mask
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mask
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},
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},
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@ -80,17 +82,34 @@ where
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}
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}
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}
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}
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pub fn set_configuration(&mut self, config: u32) -> Result<u32, Error<E>> {
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fn set_all_configurations(&mut self) -> Result<u32, Error<E>> {
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self.data = config & 0x00FFFFFF;
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match self.spi.transfer(&mut [
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match self.spi.transfer(&mut [
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((config & 0x00FF0000) >> 16) as u8,
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((self.data & 0x00FF0000) >> 16) as u8,
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((config & 0x0000FF00) >> 8) as u8,
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((self.data & 0x0000FF00) >> 8) as u8,
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((config & 0x000000FF) >> 0) as u8,
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((self.data & 0x000000FF) >> 0) as u8,
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]).map_err(Error::SPI) {
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]).map_err(Error::SPI) {
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Ok(arr) => Ok(((arr[0] as u32) << 16) | ((arr[1] as u32) << 8) | arr[2] as u32),
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Ok(arr) => Ok(self.data),
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Err(e) => Err(e),
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Err(e) => Err(e),
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}
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}
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}
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}
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pub fn set_configurations(&mut self, configs: &mut[(CFGMask, u32)]) -> Result<u32, Error<E>> {
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for config in configs.into_iter() {
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// Erase the bits in the configuration region
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self.data &= (!config.0.get_bitmask());
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// Check validity of config data
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let shifted_config: u32 = config.1 << config.0.get_shift();
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assert_eq!(shifted_config | config.0.get_bitmask(), config.0.get_bitmask());
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// Write the configuration onto local data
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self.data |= shifted_config;
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}
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// Write all configurations at the same time
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self.set_all_configurations()
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}
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pub fn get_configuration(&mut self, config_type: CFGMask) -> u8 {
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((self.data & config_type.get_bitmask()) >> config_type.get_shift()) as u8
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}
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}
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}
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impl<SPI, E> Transfer<u8> for ConfigRegister<SPI>
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impl<SPI, E> Transfer<u8> for ConfigRegister<SPI>
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20
src/main.rs
20
src/main.rs
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@ -21,7 +21,10 @@ use firmware;
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use firmware::{
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use firmware::{
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CPLD,
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CPLD,
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attenuator::Attenuator,
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attenuator::Attenuator,
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config_register::ConfigRegister,
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config_register::{
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ConfigRegister,
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CFGMask,
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},
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};
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};
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#[entry]
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#[entry]
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@ -92,7 +95,20 @@ fn main() -> ! {
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attenuator.set_channel_attenuation(2, 15.3);
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attenuator.set_channel_attenuation(2, 15.3);
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let mut config = ConfigRegister::new(parts.spi1);
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let mut config = ConfigRegister::new(parts.spi1);
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hprintln!("{}", config.set_configuration(0xDEADBEEF).unwrap()).unwrap();
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// Target configuration: 0x000FF1CE
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hprintln!("{}", config.set_configurations(&mut [
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(CFGMask::RF_SW, 0xE),
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(CFGMask::LED, 0xC),
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(CFGMask::PROFILE, 0x1),
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(CFGMask::IO_UPDATE, 0x1),
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(CFGMask::MASK_NU, 0xF),
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(CFGMask::CLK_SEL0, 0x1),
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(CFGMask::SYNC_SEL, 0x1),
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(CFGMask::RST, 0x1),
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(CFGMask::IO_RST, 0x0),
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(CFGMask::CLK_SEL1, 0x0),
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(CFGMask::DIV, 0x0),
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]).unwrap()).unwrap();
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loop {
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loop {
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nop();
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nop();
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