Merge branch 'master' of https://git.m-labs.hk/occheung/firmware-development

Cargo.lock

@@ -456,7 +456,6 @@ source = "git+https://github.com/smoltcp-rs/smoltcp.git#bdfa44270e9c59b3095b555c
 dependencies = [
  "bitflags",
  "byteorder",
- "log",
  "managed",
 ]
 

Cargo.toml

@@ -11,9 +11,8 @@ cortex-m = "0.6.2"
 cortex-m-rt = "0.6.12"
 embedded-hal = "0.2.4"
 stm32h7xx-hal = {version = "0.7.1", features = [ "stm32h743v", "rt", "unproven", "ethernet", "phy_lan8742a" ] }
-smoltcp = { version = "0.6.0", default-features = false, features = [ "ethernet", "proto-ipv4", "proto-ipv6", "socket-tcp", "log" ] }
+smoltcp = { version = "0.6.0", default-features = false, features = [ "ethernet", "proto-ipv4", "proto-ipv6", "socket-tcp" ] }
 nb = "1.0.0"
-
 embedded-nal = "0.1.0"
 minimq = { git = "https://github.com/quartiq/minimq.git", branch = "master" }
 heapless = "0.5.6"

Makefile

@@ -1,5 +0,0 @@
-fpga_config: main.rs
-	openocd -f openocd/openocd.cfg -f openocd/main.cfg
-
-main.rs: top.bin
-	cargo build --release

build.rs

@@ -2,9 +2,9 @@ use std::process::Command;
 
 fn main() {
     Command::new("python3")
-    		.arg("migen/fpga_config.py")
+    		.arg("fpga/fpga_config.py")
     		.spawn()
     		.expect("FPGA bitstream file cannot be built!");
 
-    println!("cargo:rerun-if-changed=migen/fpga_config.py")
+    println!("cargo:rerun-if-changed=fpga/fpga_config.py")
 }

fpga/fpga_config.py

@@ -0,0 +1,92 @@
+# Import built in I/O, Connectors & Platform template for Humpback
+from migen.build.platforms.sinara import humpback
+# Import migen pin record structure
+from migen.build.generic_platform import *
+from migen.fhdl.module import Module
+from migen.fhdl.specials import Instance
+from migen.genlib.io import *
+
+
+class UrukulConnector(Module):
+    def __init__(self, platform):
+        # Include extension
+        spi_mosi = [
+            ("spi_mosi", 0, Pins("B16"), IOStandard("LVCMOS33"))
+        ]
+        spi_cs = [
+            ("spi_cs", 0, Pins("B13 B14 B15"), IOStandard("LVCMOS33"))
+        ]
+        io_update = [
+            ("io_update", 0, Pins("A11"), IOStandard("LVCMOS33"))
+        ]
+
+        # Add extensions
+        platform.add_extension(spi_cs)
+        platform.add_extension(io_update)
+        platform.add_extension(spi_mosi)
+
+        # Request EEM I/O & SPI
+        eem0 = [
+            platform.request("eem0", 0),
+            platform.request("eem0", 1),
+            # Supply EEM pin with negative polarity
+            # See issue/PR: https://github.com/m-labs/migen/pull/181
+            platform.request("eem0_n", 2),
+            platform.request("eem0", 3),
+            platform.request("eem0", 4),
+            platform.request("eem0", 5),
+            platform.request("eem0", 6)
+        ]
+        spi = platform.request("spi")
+        spi_mosi = platform.request("spi_mosi")
+        spi_cs = platform.request("spi_cs")
+        led = platform.request("user_led")
+        io_update = platform.request("io_update")
+
+        assert len(spi.clk) == 1
+        assert len(spi_mosi) == 1
+        assert len(spi.miso) == 1
+        assert len(spi_cs) == 3
+        assert len(io_update) == 1
+
+        # Flip negative input to positive output
+        self.miso_n = Signal()
+
+        # Very similar setup to Diff setup for iCE40 suggested, but gave B pin instead
+        self.specials += Instance("SB_IO",
+                            p_PIN_TYPE=C(0b000001, 6),
+                            p_IO_STANDARD="SB_LVDS_INPUT",
+                            io_PACKAGE_PIN=eem0[2],
+                            o_D_IN_0=self.miso_n
+                        )
+
+        # Link EEM to SPI
+        self.comb += [
+
+            eem0[0].p.eq(spi.clk),
+            eem0[0].n.eq(~spi.clk),
+
+            eem0[1].p.eq(spi_mosi),
+            eem0[1].n.eq(~spi_mosi),
+
+            spi.miso.eq(~self.miso_n),
+
+            eem0[3].p.eq(spi_cs[0]),
+            eem0[3].n.eq(~spi_cs[0]),
+
+            eem0[4].p.eq(spi_cs[1]),
+            eem0[4].n.eq(~spi_cs[1]),
+
+            eem0[5].p.eq(spi_cs[2]),
+            eem0[5].n.eq(~spi_cs[2]),
+
+            eem0[6].p.eq(io_update),
+            eem0[6].n.eq(~io_update),
+
+            led.eq(1)
+        ]
+
+
+if __name__ == "__main__":
+    platform = humpback.Platform()
+    platform.build(UrukulConnector(platform))

migen/fpga_config.py

@@ -1,92 +0,0 @@
-# Import built in I/O, Connectors & Platform template for Humpback
-from migen.build.platforms.sinara import humpback
-# Import migen pin record structure
-from migen.build.generic_platform import *
-from migen.fhdl.module import Module
-from migen.fhdl.specials import Instance
-from migen.genlib.io import *
-
-
-class UrukulConnector(Module):
-	def __init__(self, platform):
-		# Include extension
-		spi_mosi = [
-			("spi_mosi", 0, Pins("B16"), IOStandard("LVCMOS33"))
-		]
-		spi_cs = [
-			("spi_cs", 0, Pins("B13 B14 B15"), IOStandard("LVCMOS33"))
-		]
-		io_update = [
-			("io_update", 0, Pins("A11"), IOStandard("LVCMOS33"))
-		]
-
-		# Add extensions
-		platform.add_extension(spi_cs)
-		platform.add_extension(io_update)
-		platform.add_extension(spi_mosi)
-
-		# Request EEM I/O & SPI
-		eem0 = [
-			platform.request("eem0", 0),
-			platform.request("eem0", 1),
-			# Supply EEM pin with negative polarity
-			# See issue/PR: https://github.com/m-labs/migen/pull/181
-			platform.request("eem0_n", 2),
-			platform.request("eem0", 3),
-			platform.request("eem0", 4),
-			platform.request("eem0", 5),
-			platform.request("eem0", 6)
-		]
-		spi = platform.request("spi")
-		spi_mosi = platform.request("spi_mosi")
-		spi_cs = platform.request("spi_cs")
-		led = platform.request("user_led")
-		io_update = platform.request("io_update")
-
-		assert len(spi.clk) == 1
-		assert len(spi_mosi) == 1
-		assert len(spi.miso) == 1
-		assert len(spi_cs) == 3
-		assert len(io_update) == 1
-
-		# Flip negative input to positive output
-		self.miso_n = Signal()
-
-		# Very similar setup to Diff setup for iCE40 suggested, but gave B pin instead
-		self.specials += Instance("SB_IO",
-							p_PIN_TYPE=C(0b000001, 6),
-							p_IO_STANDARD="SB_LVDS_INPUT",
-							io_PACKAGE_PIN=eem0[2],
-							o_D_IN_0=self.miso_n
-						)
-
-		# Link EEM to SPI
-		self.comb += [
-
-			eem0[0].p.eq(spi.clk),
-			eem0[0].n.eq(~spi.clk),
-
-			eem0[1].p.eq(spi_mosi),
-			eem0[1].n.eq(~spi_mosi),
-
-			spi.miso.eq(~self.miso_n),
-
-			eem0[3].p.eq(spi_cs[0]),
-			eem0[3].n.eq(~spi_cs[0]),
-
-			eem0[4].p.eq(spi_cs[1]),
-			eem0[4].n.eq(~spi_cs[1]),
-
-			eem0[5].p.eq(spi_cs[2]),
-			eem0[5].n.eq(~spi_cs[2]),
-
-			eem0[6].p.eq(io_update),
-			eem0[6].n.eq(~io_update),
-
-			led.eq(1)
-		]
-
-
-if __name__ == "__main__":
-	platform = humpback.Platform()
-	platform.build(UrukulConnector(platform))

src/dds.rs

@@ -4,6 +4,7 @@ use core::mem::size_of;
 use core::convert::TryInto;
 use heapless::Vec;
 use heapless::consts::*;
+use log::{ trace, debug, warn };
 
 /*
  *  Bitmask for all configurations (Order: CFR3, CFR2, CFR1)
@@ -634,6 +635,77 @@ where
             no_dwell_high, zero_crossing, op_mode, playback_rate)
 	}
 	
+    /*
+     *  Configure a frequency sweep RAM mode profile
+     */
+	pub unsafe fn set_frequency_sweep_profile(&mut self, profile: u8, start_addr: u16,
+        lower_boundary: f64, upper_boundary: f64, f_resolution: f64,
+        no_dwell_high: bool, op_mode: RAMOperationMode, playback_rate: f64
+    ) -> Result<(), Error<E>> {
+
+        // Check the legality of the profile setup
+        assert!(profile <= 7);
+        assert!(start_addr < 1024);
+
+        // Find out the required RAM size
+        // Frequencies may have to be repeated if the playback rate is too low
+        // Reject impossible setups
+        // E.g. Higher playback rate than f_dds_clk, insufficient RAM allocation
+        let nominal_step_rate = self.f_sys_clk/(4.0 * playback_rate);
+        if nominal_step_rate < 1.0 {
+            return Err(Error::DDSRAMError);
+        }
+
+        // TODO: Handle unfortunate scenario: step_rate / 0xFFFF gives a round number
+        // Current implmentation unnecessarily allocates 1 extra RAM space for each data
+        let duplication = (nominal_step_rate / (0xFFFF as f64)) as u64 + 1;
+
+        // Acquire the RAM size needed by multiplying duplication.
+        // All data needs to be duplicated such that a desired step_rate can be reached
+        // Return DDS RAM Error if it does not fix into the RAM
+        let span = upper_boundary - lower_boundary;
+        let data_size = if core::intrinsics::roundf64(span/f_resolution) == (span/f_resolution) {
+                (span/f_resolution) as u64 + 1
+        } else {
+                (span/f_resolution) as u64
+        };
+        let ram_size = data_size * duplication;
+
+        let end_addr = (start_addr as u64) + ram_size - 1;
+        trace!("Required RAM size: {}", ram_size);
+        if end_addr >= 1024 {
+            warn!("RAM address out of bound");
+            return Err(Error::DDSRAMError);
+        }
+
+        // Clear RAM vector, and add address byte
+        RAM_VEC.clear();
+        RAM_VEC.push(0x16)
+            .map_err(|_| Error::DDSRAMError)?;
+
+        // Drop in the data into RAM_VEC
+        for data_index in 0..data_size {
+            let freq = lower_boundary + f_resolution * (data_index as f64);
+            for _ in 0..duplication {
+                let ftw = self.frequency_to_ftw(freq);
+                RAM_VEC.push(((ftw >> 24) & 0xFF) as u8)
+                    .map_err(|_| Error::DDSRAMError)?;
+                RAM_VEC.push(((ftw >> 16) & 0xFF) as u8)
+                    .map_err(|_| Error::DDSRAMError)?;
+                RAM_VEC.push(((ftw >>  8) & 0xFF) as u8)
+                    .map_err(|_| Error::DDSRAMError)?;
+                RAM_VEC.push(((ftw >>  0) & 0xFF) as u8)
+                    .map_err(|_| Error::DDSRAMError)?;
+            }
+        }
+
+        debug!("start_addr: {}\nend_addr: {}\n, duplication: {}\n, data_size: {}\n",
+            start_addr, end_addr, duplication, data_size);
+
+        self.set_ram_profile(profile, start_addr, end_addr.try_into().unwrap(), RAMDestination::Frequency,
+            no_dwell_high, true, op_mode, playback_rate * (duplication as f64))
+    }
+
     /*
      *  Configure a RAM mode profile, w.r.t static vector (RAM_VEC)
      */
@@ -650,6 +722,7 @@ where
 
         // Calculate address step rate, and check legality
         let step_rate = (self.f_sys_clk/(4.0 * playback_rate)) as u64;
+        trace!("Setting up RAM profile, step_rate: {}", step_rate);
         if step_rate == 0 || step_rate > 0xFFFF {
             return Err(Error::DDSRAMError);
         }
@@ -729,9 +802,9 @@ where
 
     // Setter function for f_sys_clk
     // Warning: This does not setup the chip to generate this actual f_sys_clk
-	pub(crate) fn set_f_sys_clk(&mut self, f_sys_clk: f64) {
-		self.f_sys_clk = f_sys_clk;
-	}
+    // pub(crate) fn set_f_sys_clk(&mut self, f_sys_clk: f64) {
+    //     self.f_sys_clk = f_sys_clk;
+    // }
 
     // Getter function for f_sys_clk
     pub fn get_f_sys_clk(&mut self) -> f64 {

src/main.rs

@@ -1,15 +1,15 @@
 #![no_main]
 #![no_std]
-#![feature(str_strip)]
-use log::{ trace, debug, info, warn };
-use stm32h7xx_hal::hal::digital::v2::InputPin;
+#![feature(core_intrinsics)]
+
+use log::{ trace };
 use stm32h7xx_hal::gpio::Speed;
 use stm32h7xx_hal::{pac, prelude::*, spi};
 use stm32h7xx_hal::ethernet;
 
 use smoltcp as net;
 use minimq::{
-    embedded_nal::{IpAddr, Ipv4Addr, TcpStack},
+    embedded_nal::{ IpAddr, Ipv4Addr },
     MqttClient, QoS
 };
 
@@ -17,7 +17,6 @@ use cortex_m;
 use cortex_m_rt::entry;
 use rtic::cyccnt::{Instant, U32Ext};
 
-use heapless::Vec;
 use heapless::consts;
 
 #[macro_use]
@@ -106,7 +105,7 @@ fn main() -> ! {
     let gpiob = dp.GPIOB.split(ccdr.peripheral.GPIOB);
     let gpioc = dp.GPIOC.split(ccdr.peripheral.GPIOC);
     let gpiod = dp.GPIOD.split(ccdr.peripheral.GPIOD);
-	let gpioe = dp.GPIOE.split(ccdr.peripheral.GPIOE);
+    let _gpioe = dp.GPIOE.split(ccdr.peripheral.GPIOE);
     let gpiof = dp.GPIOF.split(ccdr.peripheral.GPIOF);
     let gpiog = dp.GPIOG.split(ccdr.peripheral.GPIOG);
 
@@ -207,7 +206,7 @@ fn main() -> ! {
     let spi = dp.SPI6.spi(
         (sclk, miso, mosi),
         spi::MODE_0,
-		10.mhz(),
+        2.mhz(),
         ccdr.peripheral.SPI6,
         &ccdr.clocks,
     );
@@ -220,7 +219,6 @@ fn main() -> ! {
     );
 
     urukul.reset().unwrap();
-	// info!("Test value: {}", urukul.test().unwrap());
 
     let mut mqtt_mux = MqttMux::new(urukul);
 
@@ -238,9 +236,6 @@ fn main() -> ! {
 
     let tcp_stack = NetworkStack::new(&mut net_interface, sockets);
 
-    // Case dealt: Ethernet connection break down, neither side has timeout
-    // Limitation: Timeout inequality will cause TCP socket state to desync
-    //              Probably fixed in latest smoltcp commit
     let mut client = MqttClient::<consts::U256, _>::new(
         IpAddr::V4(Ipv4Addr::new(192, 168, 1, 125)),
         "Urukul",
@@ -269,9 +264,8 @@ fn main() -> ! {
         // Process MQTT messages about Urukul/Control
         let connection = client
             .poll(|_client, topic, message, _properties| {
-                // info!("On {:?}, received: {:?}", topic, message);
                 // Why is topic a string while message is a slice?
-                mqtt_mux.process_mqtt(topic, message).is_ok();
+                mqtt_mux.process_mqtt(topic, message).unwrap();
             }).is_ok();
         
         if connection && !has_subscribed && tick {

src/nal_tcp_client.rs

@@ -56,7 +56,7 @@ impl<'a, 'b, 'c, 'n> NetworkStack<'a, 'b, 'c, 'n> {
         self.network_interface.poll_delay(
             &mut self.sockets.borrow_mut(),
             net::time::Instant::from_millis(time as i64),
-        ).map_or(1000, |next_poll_time| next_poll_time.total_millis() as u32)
+        ).map_or(0, |next_poll_time| next_poll_time.total_millis() as u32)
     }
 
     pub fn update(&mut self, time: u32) -> bool {
@@ -120,6 +120,8 @@ impl<'a, 'b, 'c, 'n> embedded_nal::TcpStack for NetworkStack<'a, 'b, 'c, 'n> {
                 internal_socket
                     .connect((address, remote.port()), self.get_ephemeral_port())
                     .map_err(|_| NetworkError::ConnectionFailure)?;
+                internal_socket
+                    .set_keep_alive(Some(net::time::Duration::from_millis(1000)));
             }
             embedded_nal::IpAddr::V6(addr) => {
                 let address = {
@@ -132,6 +134,8 @@ impl<'a, 'b, 'c, 'n> embedded_nal::TcpStack for NetworkStack<'a, 'b, 'c, 'n> {
                 internal_socket
                     .connect((address, remote.port()), self.get_ephemeral_port())
                     .map_err(|_| NetworkError::ConnectionFailure)?;
+                internal_socket
+                    .set_keep_alive(Some(net::time::Duration::from_millis(1000)));
             }
         };
 

src/urukul.rs

@@ -7,7 +7,7 @@ use crate::config_register::ConfigRegister;
 use crate::config_register::CFGMask;
 use crate::config_register::StatusMask;
 use crate::attenuator::Attenuator;
-use crate::dds::DDS;
+use crate::dds::{ DDS, RAMOperationMode };
 
 /*
  * Enum for structuring error
@@ -278,6 +278,16 @@ where
         self.dds[usize::from(channel)].set_single_tone_profile_amplitude(profile, amplitude)
     }
 
+    pub fn set_channel_frequency_sweep_profile(&mut self, channel: u8, profile: u8, start_addr: u16, lower_boundary: f64,
+        upper_boundary: f64, f_resolution: f64, playback_rate: f64) -> Result<(), Error<E>>
+    {
+        unsafe {
+            self.dds[usize::from(channel)]
+                .set_frequency_sweep_profile(profile, start_addr, lower_boundary, upper_boundary,
+                f_resolution, true, RAMOperationMode::ContinuousRecirculate, playback_rate)
+        }
+    }
+
     pub fn set_channel_sys_clk(&mut self, channel: u8, f_sys_clk: f64) -> Result<(), Error<E>> {
         self.dds[usize::from(channel)].set_sys_clk_frequency(f_sys_clk).map(|_| ())
     }
@@ -318,10 +328,9 @@ where
                 }
             }
         }
-		self.multi_dds.set_sys_clk_frequency(reported_f_sys_clk);
+        self.multi_dds.set_sys_clk_frequency(reported_f_sys_clk)?;
         self.multi_dds.set_single_tone_profile(profile, frequency, phase, amplitude)?;
-		self.invoke_io_update()?;
-		Ok(())
+        self.invoke_io_update()
     }
 
     // Generate a pulse for io_update bit in configuration register
@@ -334,5 +343,4 @@ where
             (CFGMask::IO_UPDATE, 0)
         ]).map(|_| ())
     }
-
 }