src: replace hprint with logging

eth ex: support tcp client
eth clock: init
2020-09-10 14:35:47 +08:00 · 2020-09-10 14:35:11 +08:00 · 2020-09-10 14:34:31 +08:00 · 2020-09-10 10:29:35 +08:00 · 2020-09-10 10:28:51 +08:00 · 2020-09-10 10:27:52 +08:00
18 changed files with 668 additions and 377 deletions
--- a/.gitignore
+++ b/.gitignore
@ -5,3 +5,4 @@ Cargo.lock
 target/
 **/build
 **/__pycache__
+itm.fifo
--- a/Cargo.toml
+++ b/Cargo.toml
@ -6,28 +6,26 @@ name = "firmware"
 version = "0.1.0"

 [dependencies]
-cortex-m-semihosting = "0.3.3"
 panic-halt = "0.2.0"
 cortex-m = "0.6.2"
 cortex-m-rt = "0.6.12"
 embedded-hal = "0.2.4"
 stm32h7xx-hal = {version = "0.7.1", features = [ "stm32h743v", "rt", "unproven", "ethernet", "phy_lan8742a" ] }
-smoltcp = { version = "0.6.0", default-features = false, features = [ "ethernet", "proto-ipv4", "proto-ipv6", "socket-tcp" ] }
+smoltcp = { version = "0.6.0", default-features = false, features = [ "ethernet", "proto-ipv4", "proto-ipv6", "socket-tcp", "log" ] }
 nb = "1.0.0"

-lexical-core = { version="0.7.1", features=["radix"], default-features=false }
-libm = "0.2.0"
 embedded-nal = "0.1.0"
 minimq = "0.1.0"
-enum-iterator = "0.6.0"
 heapless = "0.5.5"
-generic-array = "0.14.3"

 # Logging and Panicking
 panic-itm = "0.4.1"
 panic-semihosting = { version = "0.5.3", features = [ "exit" ] }
 cortex-m-rtic = "0.5.3"
-cortex-m-log = { version = "~0.6", features = [ "itm" ] }
+cortex-m-log = { version = "0.6.2", features = [ "itm", "log-integration", "semihosting" ] }
+cortex-m-semihosting = "0.3.3"
+log = {version = "0.4.11"}
+lazy_static = { version = "1.4.0", features = ["spin_no_std"] }

 [dependencies.scpi]
 git = "https://github.com/occheung/scpi-rs"
--- a/examples/ethernet.rs
+++ b/examples/ethernet.rs
@ -4,8 +4,8 @@
 // extern crate cortex_m_rt as rt;
 use core::sync::atomic::{AtomicU32, Ordering};

-//#[macro_use]
-//extern crate log;
+#[macro_use]
+extern crate log;

 // extern crate cortex_m;
 use panic_semihosting as _;
@ -33,8 +33,6 @@ use stm32h7xx_hal::rcc::CoreClocks;
 use stm32h7xx_hal::{pac, prelude::*, spi, stm32, stm32::interrupt};
 use Speed::*;

-use libm::round;
-
 use core::{
    str,
    fmt::Write
@ -48,6 +46,7 @@ use smoltcp::iface::{NeighborCache, EthernetInterfaceBuilder, Routes};
 use smoltcp::socket::SocketSet;
 use smoltcp::socket::{SocketHandle, TcpSocket, TcpSocketBuffer};
 use smoltcp::time::{Duration, Instant};
+// use smoltcp::log;

 // Use embedded-nal to access smoltcp
 use embedded_nal::TcpStack;
@ -101,6 +100,9 @@ use scpi::{
    scpi_system,
 };

+#[path = "util/logger.rs"]
+mod logger;
+
 /// Configure SYSTICK for 1ms timebase
 fn systick_init(syst: &mut stm32::SYST, clocks: CoreClocks) {
    let c_ck_mhz = clocks.c_ck().0 / 1_000_000;
@ -138,6 +140,8 @@ const BUFFER_SIZE: usize = 2048;
 #[entry]
 fn main() -> ! {

+    logger::semihosting_init();
+
    let mut cp = cortex_m::Peripherals::take().unwrap();
    let dp = pac::Peripherals::take().unwrap();

@ -163,8 +167,6 @@ fn main() -> ! {
    // Initialise system...
    cp.SCB.invalidate_icache();
    cp.SCB.enable_icache();
-    // TODO: ETH DMA coherence issues
-    // cp.SCB.enable_dcache(&mut cp.CPUID);
    cp.DWT.enable_cycle_counter();

    // Initialise IO...
@ -175,21 +177,15 @@ fn main() -> ! {
 	let gpioe = dp.GPIOE.split(ccdr.peripheral.GPIOE);
 	let gpiof = dp.GPIOF.split(ccdr.peripheral.GPIOF);
    let gpiog = dp.GPIOG.split(ccdr.peripheral.GPIOG);
-    // let mut link_led = gpiob.pb0.into_push_pull_output(); // LED1, green
-    // let mut status_led = gpioe.pe1.into_push_pull_output(); // LD2, yellow
-    // let mut listen_led = gpiob.pb14.into_push_pull_output(); // LD3, red
-    // link_led.set_low().ok();
-    // status_led.set_low().ok();
-    // listen_led.set_low().ok();

 	// Setup CDONE for checking
 	let fpga_cdone = gpiod.pd15.into_pull_up_input();

 	match fpga_cdone.is_high() {
-		Ok(true)	=> hprintln!("FPGA is ready."),
-		Ok(_)		=> hprintln!("FPGA is in reset state."),
-		Err(_)		=> hprintln!("Error: Cannot read C_DONE"),
-    }.unwrap();
+		Ok(true)	=> debug!("FPGA is ready."),
+		Ok(_)		=> debug!("FPGA is in reset state."),
+		Err(_)		=> debug!("Error: Cannot read C_DONE"),
+    };
    
    // Setup Urukul
 	/*
@ -279,18 +275,11 @@ fn main() -> ! {
    let mut neighbor_storage = [None; 16];
    let neighbor_cache = NeighborCache::new(&mut neighbor_storage[..]);

-    // Routes
-    let default_v4_gw = Ipv4Address::new(192, 168, 1, 1);
-    let mut routes_storage = [None; 8];
-    let mut routes = Routes::new(&mut routes_storage[..]);
-    routes.add_default_ipv4_route(default_v4_gw).unwrap();
-
    // Device? _eth_dma, as it implements phy::device
    let mut iface = EthernetInterfaceBuilder::new(_eth_dma)
            .ethernet_addr(mac_addr)
            .neighbor_cache(neighbor_cache)
            .ip_addrs(&mut ip_addrs[..])
-            .routes(routes)
            .finalize();

    // SCPI configs
@ -354,9 +343,6 @@ fn main() -> ! {

    let mut eth_up = false;

-    // Record activeness of silent socket, init as false
-    let mut silent_socket_active = false;
-
    loop {
        let _time = TIME.load(Ordering::Relaxed);
        let eth_last = eth_up;
@ -388,9 +374,9 @@ fn main() -> ! {
                }
                let result = context.run(data, &mut buf);
                if let Err(err) = result {
-                    writeln!(socket, "{}", str::from_utf8(err.get_message()).unwrap());
+                    writeln!(socket, "{}", str::from_utf8(err.get_message()).unwrap()).unwrap();
                } else {
-                    write!(socket, "{}", str::from_utf8(buf.as_slice()).unwrap());
+                    write!(socket, "{}", str::from_utf8(buf.as_slice()).unwrap()).unwrap();
                }
 		    }
 		}
--- a/examples/mqtt_client.rs
+++ b/examples/mqtt_client.rs
@ -1,6 +1,9 @@
 #![no_std]
 #![no_main]

+#[macro_use]
+extern crate log;
+
 use smoltcp as net;
 use stm32h7xx_hal::ethernet;
 use stm32h7xx_hal::{gpio::Speed, prelude::*, spi, pac};
@ -18,7 +21,7 @@ use cortex_m_rt::{
 };
 use cortex_m_semihosting::hprintln;

-use panic_halt as _;
+// use panic_halt as _;

 use rtic::cyccnt::{Instant, U32Ext};

@ -31,6 +34,9 @@ use firmware::nal_tcp_client::{NetworkStack, NetStorage, NetworkInterface};
 use firmware::{Urukul};
 use firmware::cpld::{CPLD};

+#[path = "util/logger.rs"]
+mod logger;
+
 static mut NET_STORE: NetStorage = NetStorage {
    // Placeholder for the real IP address, which is initialized at runtime.
    ip_addrs: [net::wire::IpCidr::Ipv6(
@ -61,6 +67,8 @@ macro_rules! add_socket {

 #[entry]
 fn main() -> ! {
+    // logger::semihosting_init();
+
    let mut cp = cortex_m::Peripherals::take().unwrap();
    let dp = pac::Peripherals::take().unwrap();

@ -68,19 +76,24 @@ fn main() -> ! {

    // Enable SRAM3 for the descriptor ring.
    dp.RCC.ahb2enr.modify(|_, w| w.sram3en().set_bit());
+    // Reset RCC clock
+    dp.RCC.rsr.write(|w| w.rmvf().set_bit());

-    let rcc = dp.RCC.constrain();
    let pwr = dp.PWR.constrain();
    let vos = pwr.freeze();

+    let rcc = dp.RCC.constrain();
    let ccdr = rcc
-    .sysclk(400.mhz())
-    .hclk(200.mhz())
-    .per_ck(100.mhz())
-    .pll1_q_ck(48.mhz())    // for SPI
-    .pll2_p_ck(100.mhz())
-    .pll2_q_ck(100.mhz())
-    .freeze(vos, &dp.SYSCFG);
+                .use_hse(16.mhz())
+                .sysclk(400.mhz())
+                .hclk(200.mhz())
+                .per_ck(100.mhz())
+                .pll1_q_ck(48.mhz())    // for SPI
+                .pll2_p_ck(100.mhz())
+                .pll2_q_ck(100.mhz())
+                .freeze(vos, &dp.SYSCFG);
+
+    let mut delay = cp.SYST.delay(ccdr.clocks);

    let gpioa = dp.GPIOA.split(ccdr.peripheral.GPIOA);
    let gpiob = dp.GPIOB.split(ccdr.peripheral.GPIOB);
@ -94,6 +107,8 @@ fn main() -> ! {
    yellow_led.set_low().unwrap();
    let mut red_led = gpiob.pb14.into_push_pull_output();
    red_led.set_high().unwrap();
+    let mut green_led = gpiob.pb0.into_push_pull_output();
+    green_led.set_low().unwrap();

    // Configure ethernet IO
    {
@ -177,6 +192,9 @@ fn main() -> ! {

    cp.SCB.invalidate_icache();
    cp.SCB.enable_icache();
+    // cp.SCB.clean_dcache(&mut cp.CPUID);
+    // cp.SCB.disable_dcache(&mut cp.CPUID);
+    // cp.SCB.enable_dcache(&mut cp.CPUID);

    let mut time: u32 = 0;
    let mut next_ms = Instant::now();
@ -195,7 +213,27 @@ fn main() -> ! {
    )
    .unwrap();

+    delay.delay_ms(1000_u16);
+
+    client.network_stack.update(time);
+    green_led.set_high().unwrap();
+
    loop {
+        let tick = Instant::now() > next_ms;
+
+        if tick {
+            next_ms += 400_000.cycles();
+            time += 1;
+        }
+
+        client.network_stack.update(time);
+
+        client
+            .poll(|_client, topic, message, _properties| match topic {
+                _ => info!("On '{:?}', received: {:?}", topic, message),
+            })
+            .unwrap();
+
        match client.is_connected() {
            true => {
                yellow_led.set_high().unwrap();
@ -207,19 +245,6 @@ fn main() -> ! {
            },
        };

-        client
-            .poll(|_client, topic, message, _properties| match topic {
-                _ => hprintln!("On '{:?}', received: {:?}", topic, message).unwrap(),
-            })
-            .unwrap();
-
-        let tick = Instant::now() > next_ms;
-
-        if tick {
-            next_ms += 400_000.cycles();
-            time += 1;
-        }
-
        if tick && (time % 1000) == 0 {
            client
                .publish("nucleo", "Hello, World!".as_bytes(), QoS::AtMostOnce, &[])
@ -227,10 +252,10 @@ fn main() -> ! {
        }

        // Update the TCP stack.
-        let sleep = client.network_stack.update(time);
-        if sleep {
-            //cortex_m::asm::wfi();
-            cortex_m::asm::nop();
-        }
+        // let sleep = client.network_stack.update(time);
+        // if sleep {
+        //     //cortex_m::asm::wfi();
+        //     cortex_m::asm::nop();
+        // }
    }
 }
--- a/examples/tcp_client.rs
+++ b/examples/tcp_client.rs
@ -1,179 +1,174 @@
-#![no_main]
 #![no_std]
+#![no_main]
+
+#[macro_use]
+extern crate log;
+
+#[macro_use]
+extern crate lazy_static;
+
+use smoltcp as net;
+use stm32h7xx_hal::ethernet;
+use stm32h7xx_hal::{gpio::Speed, prelude::*, spi, pac};
+use embedded_hal::{
+    blocking::spi::Transfer,
+    digital::v2::OutputPin,
+};

 use core::sync::atomic::{AtomicU32, Ordering};
+use core::fmt::Write;
+use core::str;

-// extern crate cortex_m;
-use panic_semihosting as _;
+// use heapless::{consts, String};

 use cortex_m;
-use cortex_m::asm::nop;
+use cortex_m::iprintln;
 use cortex_m_rt::{
    entry,
    exception,
 };
-use cortex_m_semihosting::hprintln;
+// use cortex_m_semihosting::hprintln;

-extern crate smoltcp;
+// use panic_halt as _;

-use stm32h7xx_hal::ethernet;
-use stm32h7xx_hal::gpio::Speed;
-use stm32h7xx_hal::hal::digital::v2::{
-    OutputPin,
-    InputPin,
+use rtic::cyccnt::{Instant, U32Ext};
+
+use log::info;
+use log::debug;
+use log::trace;
+
+use nb::block;
+
+use minimq::{
+    embedded_nal::{IpAddr, Ipv4Addr, TcpStack, SocketAddr, Mode},
+    MqttClient, QoS,
 };
-use stm32h7xx_hal::rcc::CoreClocks;
-use stm32h7xx_hal::{pac, prelude::*, spi, stm32, stm32::interrupt};
-use Speed::*;

-use libm::round;
+use firmware::nal_tcp_client::{NetworkStack, NetStorage, NetworkInterface};
+use firmware::{Urukul};
+use firmware::cpld::{CPLD};

-use core::{
-    str,
-    fmt::Write
-};
-use core::mem::uninitialized;
-
-use smoltcp::wire::{EthernetAddress, IpAddress, IpCidr, Ipv4Address};
-use smoltcp::iface::{NeighborCache, EthernetInterfaceBuilder, Routes};
-use smoltcp::socket::SocketSet;
-use smoltcp::socket::{SocketHandle, TcpSocket, TcpSocketBuffer};
-use smoltcp::time::{Duration, Instant};
-
-use embedded_nal::TcpStack;
-
-use firmware;
-use firmware::{
-	attenuator::Attenuator,
-	config_register::{
-		ConfigRegister,
-		CFGMask,
-		StatusMask,
-	},
-	dds::{
-		DDS,
-		DDSCFRMask,
-	},
-	cpld::{
-		CPLD,
-    },
-    Urukul,
-};
-use scpi::prelude::*;
-
-/// Configure SYSTICK for 1ms timebase
-fn systick_init(syst: &mut stm32::SYST, clocks: CoreClocks) {
-    let c_ck_mhz = clocks.c_ck().0 / 1_000_000;
-
-    let syst_calib = 0x3E8;
-
-    syst.set_clock_source(cortex_m::peripheral::syst::SystClkSource::Core);
-    syst.set_reload((syst_calib * c_ck_mhz) - 1);
-    syst.enable_interrupt();
-    syst.enable_counter();
-}
-
-/// ======================================================================
-/// Entry point
-/// ======================================================================
-
-/// TIME is an atomic u32 that counts milliseconds. Although not used
-/// here, it is very useful to have for network protocols
-static TIME: AtomicU32 = AtomicU32::new(0);
-
-/// Locally administered MAC address
-const MAC_ADDRESS: [u8; 6] = [0x02, 0x00, 0x11, 0x22, 0x33, 0x44];
-
-/// Ethernet descriptor rings are a global singleton
 #[link_section = ".sram3.eth"]
 static mut DES_RING: ethernet::DesRing = ethernet::DesRing::new();

-// Theoratical maximum number of socket that can be handled
-const SOCKET_COUNT: usize = 2;
+// Logging setup
+#[path = "util/logger.rs"]
+mod logger;
+#[path = "util/clock.rs"]
+mod clock;
+// End of logging setup

-// Give buffer sizes of transmitting and receiving TCP packets
-const BUFFER_SIZE: usize = 2048;
+// static TIME: AtomicU32 = AtomicU32::new(0);

-// the program entry point
 #[entry]
 fn main() -> ! {
    
+    // logger::semihosting_init();
+    let clock = clock::Clock::new();
+
    let mut cp = cortex_m::Peripherals::take().unwrap();
    let dp = pac::Peripherals::take().unwrap();

-    // Initialise power...
+    cp.DWT.enable_cycle_counter();
+
+    // Enable SRAM3 for the descriptor ring.
+    dp.RCC.ahb2enr.modify(|_, w| w.sram3en().set_bit());
+    // Reset RCC clock
+    dp.RCC.rsr.write(|w| w.rmvf().set_bit());
+
    let pwr = dp.PWR.constrain();
    let vos = pwr.freeze();

-    // Initialise SRAM3
-    dp.RCC.ahb2enr.modify(|_, w| w.sram3en().set_bit());
-
-    // Initialise clocks...
    let rcc = dp.RCC.constrain();
    let ccdr = rcc
-        .sys_ck(200.mhz())
-        .hclk(200.mhz())
-        .pll1_r_ck(100.mhz())   // for TRACECK
-        .pll1_q_ck(48.mhz())    // for SPI
-        .freeze(vos, &dp.SYSCFG);
+                .use_hse(8.mhz())
+                .sysclk(400.mhz())
+                // .hclk(200.mhz())
+                // .per_ck(100.mhz())
+                .pll1_q_ck(48.mhz())    // for SPI
+                // .pll1_r_ck(400.mhz())   // for TRACECK
+                // .pll2_p_ck(100.mhz())
+                // .pll2_q_ck(100.mhz())
+                .freeze(vos, &dp.SYSCFG);

-    // Get the delay provider.
-    let delay = cp.SYST.delay(ccdr.clocks);
+    let mut delay = cp.SYST.delay(ccdr.clocks);

-    // Initialise system...
-    cp.SCB.invalidate_icache();
-    cp.SCB.enable_icache();
-    // TODO: ETH DMA coherence issues
-    // cp.SCB.enable_dcache(&mut cp.CPUID);
-    cp.DWT.enable_cycle_counter();
-
-    // Initialise IO...
    let gpioa = dp.GPIOA.split(ccdr.peripheral.GPIOA);
    let gpiob = dp.GPIOB.split(ccdr.peripheral.GPIOB);
    let gpioc = dp.GPIOC.split(ccdr.peripheral.GPIOC);
-	let gpiod = dp.GPIOD.split(ccdr.peripheral.GPIOD);
-	let gpioe = dp.GPIOE.split(ccdr.peripheral.GPIOE);
-	let gpiof = dp.GPIOF.split(ccdr.peripheral.GPIOF);
+    let gpiod = dp.GPIOD.split(ccdr.peripheral.GPIOD);
+    let gpioe = dp.GPIOE.split(ccdr.peripheral.GPIOE);
+    let gpiof = dp.GPIOF.split(ccdr.peripheral.GPIOF);
    let gpiog = dp.GPIOG.split(ccdr.peripheral.GPIOG);
-    // let mut link_led = gpiob.pb0.into_push_pull_output(); // LED1, green
-    // let mut status_led = gpioe.pe1.into_push_pull_output(); // LD2, yellow
-    // let mut listen_led = gpiob.pb14.into_push_pull_output(); // LD3, red
-    // link_led.set_low().ok();
-    // status_led.set_low().ok();
-    // listen_led.set_low().ok();

-	// Setup CDONE for checking
-	let fpga_cdone = gpiod.pd15.into_pull_up_input();
+    let mut yellow_led = gpioe.pe1.into_push_pull_output();
+    yellow_led.set_low().unwrap();
+    let mut red_led = gpiob.pb14.into_push_pull_output();
+    red_led.set_high().unwrap();
+    let mut green_led = gpiob.pb0.into_push_pull_output();
+    green_led.set_low().unwrap();

-	match fpga_cdone.is_high() {
-		Ok(true)	=> hprintln!("FPGA is ready."),
-		Ok(_)		=> hprintln!("FPGA is in reset state."),
-		Err(_)		=> hprintln!("Error: Cannot read C_DONE"),
-    }.unwrap();
+    // Configure ethernet IO
+    {
+        let _rmii_refclk = gpioa.pa1.into_alternate_af11().set_speed(Speed::VeryHigh);
+        let _rmii_mdio = gpioa.pa2.into_alternate_af11().set_speed(Speed::VeryHigh);
+        let _rmii_mdc = gpioc.pc1.into_alternate_af11().set_speed(Speed::VeryHigh);
+        let _rmii_crs_dv = gpioa.pa7.into_alternate_af11().set_speed(Speed::VeryHigh);
+        let _rmii_rxd0 = gpioc.pc4.into_alternate_af11().set_speed(Speed::VeryHigh);
+        let _rmii_rxd1 = gpioc.pc5.into_alternate_af11().set_speed(Speed::VeryHigh);
+        let _rmii_tx_en = gpiog.pg11.into_alternate_af11().set_speed(Speed::VeryHigh);
+        let _rmii_txd0 = gpiog.pg13.into_alternate_af11().set_speed(Speed::VeryHigh);
+        let _rmii_txd1 = gpiob.pb13.into_alternate_af11().set_speed(Speed::VeryHigh);
+    }

-    // Setup Urukul
-	/*
-	 *	Using SPI1, AF5
-	 *  SCLK -> PA5
-	 *	MOSI -> PB5
-	 *	MISO -> PA6
-	 *	CS -> 0: PB12, 1: PA15, 2: PC7
-	 */
+    // Configure ethernet
+    let mac_addr = net::wire::EthernetAddress([0xAC, 0x6F, 0x7A, 0xDE, 0xD6, 0xC8]);
+    let (eth_dma, _eth_mac) = unsafe {
+        ethernet::new_unchecked(
+            dp.ETHERNET_MAC,
+            dp.ETHERNET_MTL,
+            dp.ETHERNET_DMA,
+            &mut DES_RING,
+            mac_addr.clone(),
+        )
+    };

+    unsafe { ethernet::enable_interrupt() }
+    
+    let mut ip_addrs = [net::wire::IpCidr::new(net::wire::IpAddress::v4(192, 168, 1, 200), 24)];
+
+    let mut neighbor_cache_entries = [None; 8];
+    let mut neighbor_cache = net::iface::NeighborCache::new(&mut neighbor_cache_entries[..]);
+    // neighbor_cache.fill(
+    //     net::wire::IpAddress::v4(192, 168, 1, 125),
+    //     net::wire::EthernetAddress([0x2C, 0xF0, 0x5D, 0x26, 0xB8, 0x2F]),
+    //     clock.elapsed(),
+    // );
+
+    let mut net_interface = net::iface::EthernetInterfaceBuilder::new(eth_dma)
+        .ethernet_addr(mac_addr)
+        .neighbor_cache(neighbor_cache)
+        .ip_addrs(&mut ip_addrs[..])
+        .finalize();
+
+    /*
+     *	Using SPI1, AF5
+     *  SCLK -> PA5
+     *	MOSI -> PB5
+     *	MISO -> PA6
+     *	CS -> 0: PB12, 1: PA15, 2: PC7
+     *  I/O_Update -> PB15
+     */
    let sclk = gpioa.pa5.into_alternate_af5();
    let mosi = gpiob.pb5.into_alternate_af5();
    let miso = gpioa.pa6.into_alternate_af5();

-
    let (cs0, cs1, cs2) = (
        gpiob.pb12.into_push_pull_output(),
        gpioa.pa15.into_push_pull_output(),
        gpioc.pc7.into_push_pull_output(),
    );

-    /*
-     *	I/O_Update -> PB15
-     */
    let io_update = gpiob.pb15.into_push_pull_output();     

    let spi = dp.SPI1.spi(
@ -184,201 +179,93 @@ fn main() -> ! {
        &ccdr.clocks,
    );

-    let switch = CPLD::new(spi, (cs0, cs1, cs2), io_update);
-    let parts = switch.split();
-    let mut urukul = Urukul::new(
+    let cpld = CPLD::new(spi, (cs0, cs1, cs2), io_update);
+    let parts = cpld.split();
+
+    let urukul = Urukul::new(
        parts.spi1, parts.spi2, parts.spi3, parts.spi4, parts.spi5, parts.spi6, parts.spi7,
        [25_000_000, 25_000_000, 25_000_000, 25_000_000]
    );

-    // Setup ethernet pins
-    setup_ethernet_pins(
-        gpioa.pa1, gpioa.pa2, gpioc.pc1, gpioa.pa7, gpioc.pc4,
-        gpioc.pc5, gpiog.pg11, gpiog.pg13, gpiob.pb13
-    );
+    cp.SCB.invalidate_icache();
+    cp.SCB.enable_icache();

-    // Initialise ethernet...
-    assert_eq!(ccdr.clocks.hclk().0, 200_000_000); // HCLK 200MHz
-    assert_eq!(ccdr.clocks.pclk1().0, 100_000_000); // PCLK 100MHz
-    assert_eq!(ccdr.clocks.pclk2().0, 100_000_000); // PCLK 100MHz
-    assert_eq!(ccdr.clocks.pclk4().0, 100_000_000); // PCLK 100MHz
+    // let mut time: u32 = 0;
+    // let mut next_ms = Instant::now();

-    let mac_addr = smoltcp::wire::EthernetAddress::from_bytes(&MAC_ADDRESS);
-    let (_eth_dma, mut eth_mac) = unsafe {
-        ethernet::new_unchecked(
-            dp.ETHERNET_MAC,
-            dp.ETHERNET_MTL,
-            dp.ETHERNET_DMA,
-            &mut DES_RING,
-            mac_addr.clone(),
-        )
+    // next_ms += 400_000.cycles();
+
+    let mut socket_set_entries: [_; 8] = Default::default();
+    let mut sockets = net::socket::SocketSet::new(&mut socket_set_entries[..]);
+
+    let mut rx_storage = [0; 4096];
+    let mut tx_storage = [0; 4096];
+
+    let tcp_socket = {
+        let tx_buffer = net::socket::TcpSocketBuffer::new(&mut tx_storage[..]);
+        let rx_buffer = net::socket::TcpSocketBuffer::new(&mut rx_storage[..]);
+
+        net::socket::TcpSocket::new(tx_buffer, rx_buffer)
    };
-    unsafe {
-        ethernet::enable_interrupt();
-        cp.NVIC.set_priority(stm32::Interrupt::ETH, 196); // Mid prio
-        cortex_m::peripheral::NVIC::unmask(stm32::Interrupt::ETH);
+    let handle = sockets.add(tcp_socket);
+
+    delay.delay_ms(2000_u16);
+    green_led.set_high().unwrap();
+
+    {
+        let mut socket = sockets.get::<net::socket::TcpSocket>(handle);
+        socket.connect((net::wire::IpAddress::v4(192, 168, 1, 125), 1883), 49500).unwrap();
+        debug!("connect!");
    }

-    // ----------------------------------------------------------
-    // Begin periodic tasks
+    yellow_led.set_low().unwrap();
+    red_led.set_high().unwrap();

-    systick_init(&mut delay.free(), ccdr.clocks);
-    unsafe {
-        cp.SCB.shpr[15 - 4].write(128);
-    } // systick exception priority
-
-    // ----------------------------------------------------------
-    // Main application loop
-
-    // Setup addresses, maybe not MAC?
-    // MAC is set up in prior
-    let local_addr = IpAddress::v4(192, 168, 1, 200);
-    let mut ip_addrs = [IpCidr::new(local_addr, 24)];
-
-    // let neighbor_cache = NeighborCache::new(BTreeMap::new());
-    let mut neighbor_storage = [None; 16];
-    let neighbor_cache = NeighborCache::new(&mut neighbor_storage[..]);
-
-    // Routes
-    let default_v4_gw = Ipv4Address::new(192, 168, 1, 1);
-    let mut routes_storage = [None; 8];
-    let mut routes = Routes::new(&mut routes_storage[..]);
-    routes.add_default_ipv4_route(default_v4_gw).unwrap();
-
-    // Device? _eth_dma, as it implements phy::device
-    let mut iface = EthernetInterfaceBuilder::new(_eth_dma)
-            .ethernet_addr(mac_addr)
-            .neighbor_cache(neighbor_cache)
-            .ip_addrs(&mut ip_addrs[..])
-            .routes(routes)
-            .finalize();
-
-    // SCPI configs
-    // Device was declared in prior
-
-    // let mut errors = ArrayErrorQueue::<[Error; 10]>::new();
-    // let mut context = Context::new(&mut urukul, &mut errors, TREE);
-
-    // //Response bytebuffer
-    // let mut buf = ArrayVecFormatter::<[u8; 256]>::new();
-
-    // SCPI configs END
-
-    // TCP socket
-    let server_socket = {
-        static mut server_rx_storage :[u8; BUFFER_SIZE] = [0; BUFFER_SIZE];
-        static mut server_tx_storage :[u8; BUFFER_SIZE] = [0; BUFFER_SIZE];
-        let server_rx_buffer = TcpSocketBuffer::new( unsafe { &mut server_rx_storage[..] } );
-        let server_tx_buffer = TcpSocketBuffer::new( unsafe { &mut server_tx_storage[..] } );
-        TcpSocket::new(server_rx_buffer, server_tx_buffer)
-    };
-
-    // Setup a silent socket
-    let client_socket = {
-        static mut client_rx_storage :[u8; BUFFER_SIZE] = [0; BUFFER_SIZE];
-        static mut client_tx_storage :[u8; BUFFER_SIZE] = [0; BUFFER_SIZE];
-        let client_rx_buffer = TcpSocketBuffer::new( unsafe { &mut client_rx_storage[..] } );
-        let client_tx_buffer = TcpSocketBuffer::new( unsafe { &mut client_tx_storage[..] } );
-        TcpSocket::new(client_rx_buffer, client_tx_buffer)
-    };
-
-    // Socket storage
-    let mut sockets_storage: [_; 2] = Default::default();
-
-    let mut socket_set = SocketSet::new(&mut sockets_storage[..]);
-    let server_handle = socket_set.add(server_socket);
-    let client_handle = socket_set.add(client_socket);
+    let mut green = true;

    loop {
-        let _time = TIME.load(Ordering::Relaxed);
-        match iface.poll(&mut socket_set, Instant::from_millis(_time as i64)) {
-            Ok(_) => {
-                // hprintln!("Ethernet up").unwrap();
-            },
+        // let timestamp = net::time::Instant::from_millis(TIME.load(Ordering::Relaxed) as i64);
+        match net_interface.poll(&mut sockets, clock.elapsed()) {
+            Ok(_) => {},
            Err(e) => {
-                hprintln!("Ethernet down!").unwrap();
-            },
-        };
-
-	    // Conenct to TCP server through port 49500
-        {
-            let mut socket = socket_set.get::<TcpSocket>(server_handle);
-            if !socket.is_active() && !socket.is_listening(){
-                socket.listen(7777).unwrap();
-                hprintln!("Server listening").unwrap();
-            }
-
-            // hprintln!("listener state :{}", socket.state()).unwrap();
-
-            if socket.can_recv() {
-                hprintln!("{:?}", str::from_utf8(socket.recv(|data| {
-                    (data.len(), data)
-                }).unwrap()).unwrap()).unwrap();
+                debug!("poll error: {}", e);
            }
        }

        {
-            let mut socket = socket_set.get::<TcpSocket>(client_handle);
-            if !socket.is_open() {
-                socket.abort();
+            let mut socket = sockets.get::<net::socket::TcpSocket>(handle);
+
+            if socket.may_recv() {
+                yellow_led.set_high().unwrap();
+                red_led.set_low().unwrap();
+                let data = socket.recv(|data| {
+                    (data.len(), data)
+                }).unwrap();
+                if socket.can_send() {
+                    socket.send_slice("response".as_bytes()).unwrap();
+                }
+            }
+            if socket.may_send() {
+                yellow_led.set_high().unwrap();
+                red_led.set_low().unwrap();
+                debug!("close");
                socket.close();
-                hprintln!("reset state: {}", socket.state()).unwrap();
-                socket.connect((IpAddress::v4(192, 168, 1, 200), 1883),
-                (IpAddress::Unspecified, 45000)).unwrap();
-                hprintln!("post connect state: {}", socket.state()).unwrap();
            }
+        }

-            // hprintln!("client state: {}", socket.state()).unwrap();
-
-            if socket.can_send() {
-                socket.send_slice(b"regards from socket").unwrap();
-            }
+        match net_interface.poll_delay(&sockets, clock.elapsed()) {
+            Some(net::time::Duration {millis :0}) => debug!("resuming"),
+            Some(time_delay) => {
+                info!("sleeping for {} ms", time_delay);
+                // green_led.set_low().unwrap();
+                // delay.delay_ms(time_delay.total_millis() as u32);
+                // green_led.set_high().unwrap();
+                clock.advance(time_delay)
+            },
+            None => {
+                // delay.delay_ms(1_u32);
+                clock.advance(net::time::Duration::from_millis(1))
+            },
        }
    }
 }
-
-use stm32h7xx_hal::gpio::{
-    gpioa::{PA1, PA2, PA7},
-    gpiob::{PB13},
-    gpioc::{PC1, PC4, PC5},
-    gpiog::{PG11, PG13},
-    Speed::VeryHigh,
-};
-
-/*
- *  Migrated ethernet setup pins
- */
-pub fn setup_ethernet_pins<REF_CLK, MDIO, MDC, CRS_DV, RXD0, RXD1, TX_EN, TXD0, TXD1>(
-    pa1: PA1<REF_CLK>, pa2: PA2<MDIO>, pc1: PC1<MDC>, pa7: PA7<CRS_DV>, pc4: PC4<RXD0>,
-    pc5: PC5<RXD1>, pg11: PG11<TX_EN>, pg13: PG13<TXD0>, pb13: PB13<TXD1>
-) {
-    pa1.into_alternate_af11().set_speed(VeryHigh);
-    pa2.into_alternate_af11().set_speed(VeryHigh);
-    pc1.into_alternate_af11().set_speed(VeryHigh);
-    pa7.into_alternate_af11().set_speed(VeryHigh);
-    pc4.into_alternate_af11().set_speed(VeryHigh);
-    pc5.into_alternate_af11().set_speed(VeryHigh);
-    pg11.into_alternate_af11().set_speed(VeryHigh);
-    pg13.into_alternate_af11().set_speed(VeryHigh);
-    pb13.into_alternate_af11().set_speed(VeryHigh);
-}
-
-#[interrupt]
-fn ETH() {
-    unsafe { ethernet::interrupt_handler() }
-}
-
-#[exception]
-fn SysTick() {
-    TIME.fetch_add(1, Ordering::Relaxed);
-}
-
-#[exception]
-fn HardFault(ef: &cortex_m_rt::ExceptionFrame) -> ! {
-    panic!("HardFault at {:#?}", ef);
-}
-
-#[exception]
-fn DefaultHandler(irqn: i16) {
-    panic!("Unhandled exception (IRQn = {})", irqn);
-}
--- a/examples/util/clock.rs
+++ b/examples/util/clock.rs
@ -0,0 +1,19 @@
+use smoltcp::time::{Duration, Instant};
+use core::cell::Cell;
+
+#[derive(Debug)]
+pub struct Clock(Cell<Instant>);
+
+impl Clock {
+    pub fn new() -> Clock {
+        Clock(Cell::new(Instant::from_millis(0)))
+    }
+
+    pub fn advance(&self, duration: Duration) {
+        self.0.set(self.0.get() + duration)
+    }
+
+    pub fn elapsed(&self) -> Instant {
+        self.0.get()
+    }
+}
--- a/examples/util/logger.rs
+++ b/examples/util/logger.rs
@ -0,0 +1,96 @@
+// Enables ITM
+pub unsafe fn enable_itm(
+    dbgmcu: &stm32h7xx_hal::stm32::DBGMCU,
+    dcb: &mut cortex_m::peripheral::DCB,
+    itm: &mut cortex_m::peripheral::ITM
+) {
+    // ARMv7-M DEMCR: Set TRCENA. Enables DWT and ITM units
+    //unsafe { *(0xE000_EDFC as *mut u32) |= 1 << 24 };
+    dcb.enable_trace();
+
+    // Ensure debug blocks are clocked before interacting with them
+    dbgmcu.cr.modify(|_, w| {
+        w.d1dbgcken()
+            .set_bit()
+            .d3dbgcken()
+            .set_bit()
+            .traceclken()
+            .set_bit()
+            .dbgsleep_d1()
+            .set_bit()
+    });
+
+    // SWO: Unlock
+    *(0x5c00_3fb0 as *mut u32) = 0xC5ACCE55;
+    // SWTF: Unlock
+    *(0x5c00_4fb0 as *mut u32) = 0xC5ACCE55;
+
+    // SWO CODR Register: Set SWO speed
+    *(0x5c00_3010 as *mut _) = 400 - 1;
+
+    // SWO SPPR Register:
+    // 1 = Manchester
+    // 2 = NRZ
+    *(0x5c00_30f0 as *mut _) = 2;
+
+    // SWTF Trace Funnel: Enable for CM7
+    *(0x5c00_4000 as *mut u32) |= 1;
+
+    // ITM: Unlock
+    itm.lar.write(0xC5ACCE55);
+    // ITM Trace Enable Register: Enable lower 8 stimulus ports
+    itm.ter[0].write(1);
+    // ITM Trace Control Register: Enable ITM
+    itm.tcr.write(
+        (0b000001 << 16) | // TraceBusID
+        (1 << 3) | // enable SWO output
+        (1 << 0), // enable the ITM
+    );
+}
+
+// use panic_itm as _;
+
+use lazy_static::lazy_static;
+use log::LevelFilter;
+
+pub use cortex_m_log::log::Logger;
+
+use cortex_m_log::{
+    destination::Itm as ItmDest,
+    printer::itm::InterruptSync,
+    modes::InterruptFree,
+    printer::itm::ItmSync
+};
+
+lazy_static! {
+    static ref LOGGER: Logger<ItmSync<InterruptFree>> = Logger {
+        level: LevelFilter::Debug,
+        inner: unsafe {
+            InterruptSync::new(
+                ItmDest::new(cortex_m::Peripherals::steal().ITM)
+            )
+        },
+    };
+}
+
+pub fn init() {
+    cortex_m_log::log::init(&LOGGER).unwrap();
+}
+
+use panic_semihosting as _;
+
+use cortex_m_log::printer::semihosting;
+use cortex_m_log::printer::semihosting::Semihosting;
+use cortex_m_log::modes::InterruptOk;
+use cortex_m_semihosting::hio::HStdout;
+
+lazy_static! {
+    static ref HLOGGER: Logger<Semihosting<InterruptOk, HStdout>> = Logger {
+        level: LevelFilter::Trace,
+        inner: semihosting::InterruptOk::<_>::stdout().expect("Get Semihosting stdout"),
+    };
+}
+
+pub fn semihosting_init() {
+    cortex_m_log::log::init(&HLOGGER).unwrap();
+}
--- a/gdb_config/openocd.gdb
+++ b/gdb_config/openocd.gdb
@ -11,11 +11,10 @@ break DefaultHandler
 break HardFault
 break rust_begin_unwind

-# situational break points: only enable for fpga_config example
-# break examples/fpga_config.rs:126
-
 # print using semihosting, slow af
 monitor arm semihosting enable
+# monitor tpiu config internal itm.fifo uart off 400000000
+# monitor itm port 0 on

 # flash the program to STM32
 load
--- a/openocd/openocd.cfg
+++ b/openocd/openocd.cfg
@ -0,0 +1,4 @@
+source [find interface/stlink.cfg]
+transport select hla_swd
+source [find openocd/stm32h7x_dual_bank-itm_fix.cfg]
+reset_config srst_only
--- a/openocd/stm32h7x-itm_fix.cfg
+++ b/openocd/stm32h7x-itm_fix.cfg
@ -0,0 +1,280 @@
+# This is a custom version of the config that has the ITM fixed.
+# The official version can be used again when https://sourceforge.net/p/openocd/tickets/266/ has been dealt with.
+
+
+
+# script for stm32h7x family
+
+#
+# stm32h7 devices support both JTAG and SWD transports.
+#
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME stm32h7x
+}
+
+if { [info exists DUAL_BANK] } {
+	set $_CHIPNAME.DUAL_BANK $DUAL_BANK
+	unset DUAL_BANK
+} else {
+	set $_CHIPNAME.DUAL_BANK 0
+}
+
+if { [info exists DUAL_CORE] } {
+	set $_CHIPNAME.DUAL_CORE $DUAL_CORE
+	unset DUAL_CORE
+} else {
+	set $_CHIPNAME.DUAL_CORE 0
+}
+
+# Issue a warning when hla is used, and fallback to single core configuration
+if { [set $_CHIPNAME.DUAL_CORE] && [using_hla] } {
+	echo "Warning : hla does not support multicore debugging"
+	set $_CHIPNAME.DUAL_CORE 0
+}
+
+if { [info exists USE_CTI] } {
+	set $_CHIPNAME.USE_CTI $USE_CTI
+	unset USE_CTI
+} else {
+	set $_CHIPNAME.USE_CTI 0
+}
+
+# Issue a warning when DUAL_CORE=0 and USE_CTI=1, and fallback to USE_CTI=0
+if { ![set $_CHIPNAME.DUAL_CORE] && [set $_CHIPNAME.USE_CTI] } {
+	echo "Warning : could not use CTI with a single core device, CTI is disabled"
+	set $_CHIPNAME.USE_CTI 0
+}
+
+set _ENDIAN little
+
+# Work-area is a space in RAM used for flash programming
+# By default use 64kB
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x10000
+}
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   if { [using_jtag] } {
+	  set _CPUTAPID 0x6ba00477
+   } {
+      set _CPUTAPID 0x6ba02477
+   }
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+if {[using_jtag]} {
+ swj_newdap $_CHIPNAME bs -irlen 5
+}
+
+if {![using_hla]} {
+	# STM32H7 provides an APB-AP at access port 2, which allows the access to
+	# the debug and trace features on the system APB System Debug Bus (APB-D).
+	target create $_CHIPNAME.ap2 mem_ap -dap $_CHIPNAME.dap -ap-num 2
+}
+
+target create $_CHIPNAME.cpu0 cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap -ap-num 0
+
+$_CHIPNAME.cpu0 configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+flash bank $_CHIPNAME.bank1.cpu0 stm32h7x 0x08000000 0 0 0 $_CHIPNAME.cpu0
+
+if {[set $_CHIPNAME.DUAL_BANK]} {
+	flash bank $_CHIPNAME.bank2.cpu0 stm32h7x 0x08100000 0 0 0 $_CHIPNAME.cpu0
+}
+
+if {[set $_CHIPNAME.DUAL_CORE]} {
+	target create $_CHIPNAME.cpu1 cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap -ap-num 3
+
+	$_CHIPNAME.cpu1 configure -work-area-phys 0x38000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+	flash bank $_CHIPNAME.bank1.cpu1 stm32h7x 0x08000000 0 0 0 $_CHIPNAME.cpu1
+
+	if {[set $_CHIPNAME.DUAL_BANK]} {
+		flash bank $_CHIPNAME.bank2.cpu1 stm32h7x 0x08100000 0 0 0 $_CHIPNAME.cpu1
+	}
+}
+
+# Make sure that cpu0 is selected
+targets $_CHIPNAME.cpu0
+
+# Clock after reset is HSI at 64 MHz, no need of PLL
+adapter speed 1800
+
+adapter srst delay 100
+if {[using_jtag]} {
+ jtag_ntrst_delay 100
+}
+
+# use hardware reset
+#
+# The STM32H7 does not support connect_assert_srst mode because the AXI is
+# unavailable while SRST is asserted, and that is used to access the DBGMCU
+# component at 0x5C001000 in the examine-end event handler.
+#
+# It is possible to access the DBGMCU component at 0xE00E1000 via AP2 instead
+# of the default AP0, and that works with SRST asserted; however, nonzero AP
+# usage does not work with HLA, so is not done by default. That change could be
+# made in a local configuration file if connect_assert_srst mode is needed for
+# a specific application and a non-HLA adapter is in use.
+reset_config srst_only srst_nogate
+
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to
+   # perform a soft reset
+	$_CHIPNAME.cpu0 cortex_m reset_config sysresetreq
+
+	if {[set $_CHIPNAME.DUAL_CORE]} {
+		$_CHIPNAME.cpu1 cortex_m reset_config sysresetreq
+	}
+
+   # Set CSW[27], which according to ARM ADI v5 appendix E1.4 maps to AHB signal
+   # HPROT[3], which according to AMBA AHB/ASB/APB specification chapter 3.7.3
+   # makes the data access cacheable. This allows reading and writing data in the
+   # CPU cache from the debugger, which is far more useful than going straight to
+   # RAM when operating on typical variables, and is generally no worse when
+   # operating on special memory locations.
+   $_CHIPNAME.dap apcsw 0x08000000 0x08000000
+}
+
+$_CHIPNAME.cpu0 configure -event examine-end {
+	# Enable D3 and D1 DBG clocks
+	# DBGMCU_CR |= D3DBGCKEN | D1DBGCKEN
+	stm32h7x_dbgmcu_mmw 0x004 0x00600000 0
+
+	# Enable debug during low power modes (uses more power)
+	# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP in D3, D2 & D1 Domains
+	stm32h7x_dbgmcu_mmw 0x004 0x00000007 0
+
+	# Stop watchdog counters during halt
+	# DBGMCU_APB3FZ1 |= WWDG1
+	stm32h7x_dbgmcu_mmw 0x034 0x00000040 0
+	# DBGMCU_APB1LFZ1 |= WWDG2
+	stm32h7x_dbgmcu_mmw 0x03C 0x00000800 0
+	# DBGMCU_APB4FZ1 |= WDGLSD1 | WDGLSD2
+	stm32h7x_dbgmcu_mmw 0x054 0x000C0000 0
+}
+
+$_CHIPNAME.cpu0 configure -event trace-config {
+	# Set TRACECLKEN; TRACE_MODE is set to async; when using sync
+	# change this value accordingly to configure trace pins
+	# assignment
+	stm32h7x_dbgmcu_mmw 0x004 0x00100000 0
+}
+
+$_CHIPNAME.cpu0 configure -event reset-init {
+	# Clock after reset is HSI at 64 MHz, no need of PLL
+	adapter speed 4000
+}
+
+if {[set $_CHIPNAME.DUAL_CORE]} {
+	$_CHIPNAME.cpu1 configure -event examine-end {
+		# get _CHIPNAME from the current target
+		set _CHIPNAME [regsub ".cpu\\d$" [target current] ""]
+		global $_CHIPNAME.USE_CTI
+
+		# Stop watchdog counters during halt
+		# DBGMCU_APB3FZ2 |= WWDG1
+		stm32h7x_dbgmcu_mmw 0x038 0x00000040 0
+		# DBGMCU_APB1LFZ2 |= WWDG2
+		stm32h7x_dbgmcu_mmw 0x040 0x00000800 0
+		# DBGMCU_APB4FZ2 |= WDGLSD1 | WDGLSD2
+		stm32h7x_dbgmcu_mmw 0x058 0x000C0000 0
+
+		if {[set $_CHIPNAME.USE_CTI]} {
+			stm32h7x_cti_start
+		}
+	}
+}
+
+# like mrw, but with target selection
+proc stm32h7x_mrw {used_target reg} {
+	set value ""
+	$used_target mem2array value 32 $reg 1
+	return $value(0)
+}
+
+# like mmw, but with target selection
+proc stm32h7x_mmw {used_target reg setbits clearbits} {
+	set old [stm32h7x_mrw $used_target $reg]
+	set new [expr ($old & ~$clearbits) | $setbits]
+	$used_target mww $reg $new
+}
+
+# mmw for dbgmcu component registers, it accepts the register offset from dbgmcu base
+# this procedure will use the mem_ap on AP2 whenever possible
+proc stm32h7x_dbgmcu_mmw {reg_offset setbits clearbits} {
+	# use $_CHIPNAME.ap2 if possible, and use the proper dbgmcu base address
+	if {![using_hla]} {
+		# get _CHIPNAME from the current target
+		set _CHIPNAME [regsub ".(cpu|ap)\\d*$" [target current] ""]
+		set used_target $_CHIPNAME.ap2
+		set reg_addr [expr 0xE00E1000 + $reg_offset]
+	} {
+		set used_target [target current]
+		set reg_addr [expr 0x5C001000 + $reg_offset]
+	}
+
+	stm32h7x_mmw $used_target $reg_addr $setbits $clearbits
+}
+
+if {[set $_CHIPNAME.USE_CTI]} {
+	# create CTI instances for both cores
+	cti create $_CHIPNAME.cti0 -dap $_CHIPNAME.dap -ap-num 0 -ctibase 0xE0043000
+	cti create $_CHIPNAME.cti1 -dap $_CHIPNAME.dap -ap-num 3 -ctibase 0xE0043000
+
+	$_CHIPNAME.cpu0 configure -event halted { stm32h7x_cti_prepare_restart_all }
+	$_CHIPNAME.cpu1 configure -event halted { stm32h7x_cti_prepare_restart_all }
+
+	$_CHIPNAME.cpu0 configure -event debug-halted { stm32h7x_cti_prepare_restart_all }
+	$_CHIPNAME.cpu1 configure -event debug-halted { stm32h7x_cti_prepare_restart_all }
+
+	proc stm32h7x_cti_start {} {
+		# get _CHIPNAME from the current target
+		set _CHIPNAME [regsub ".cpu\\d$" [target current] ""]
+
+		# Configure Cores' CTIs to halt each other
+		# TRIGIN0 (DBGTRIGGER) and TRIGOUT0 (EDBGRQ) at CTM_CHANNEL_0
+		$_CHIPNAME.cti0 write INEN0 0x1
+		$_CHIPNAME.cti0 write OUTEN0 0x1
+		$_CHIPNAME.cti1 write INEN0 0x1
+		$_CHIPNAME.cti1 write OUTEN0 0x1
+
+		# enable CTIs
+		$_CHIPNAME.cti0 enable on
+		$_CHIPNAME.cti1 enable on
+	}
+
+	proc stm32h7x_cti_stop {} {
+		# get _CHIPNAME from the current target
+		set _CHIPNAME [regsub ".cpu\\d$" [target current] ""]
+
+		$_CHIPNAME.cti0 enable off
+		$_CHIPNAME.cti1 enable off
+	}
+
+	proc stm32h7x_cti_prepare_restart_all {} {
+		stm32h7x_cti_prepare_restart cti0
+		stm32h7x_cti_prepare_restart cti1
+	}
+
+	proc stm32h7x_cti_prepare_restart {cti} {
+		# get _CHIPNAME from the current target
+		set _CHIPNAME [regsub ".cpu\\d$" [target current] ""]
+
+		# Acknowlodge EDBGRQ at TRIGOUT0
+		$_CHIPNAME.$cti write INACK 0x01
+		$_CHIPNAME.$cti write INACK 0x00
+	}
+}
--- a/openocd/stm32h7x_dual_bank-itm_fix.cfg
+++ b/openocd/stm32h7x_dual_bank-itm_fix.cfg
@ -0,0 +1,6 @@
+# script for stm32h7x family (dual flash bank)
+
+# STM32H7xxxI 2Mo have a dual bank flash.
+set DUAL_BANK 1
+
+source [find openocd/stm32h7x-itm_fix.cfg]
--- a/shell.nix
+++ b/shell.nix
@ -16,7 +16,7 @@ let
 	'';

 	runOpenOcdBlock = writeShellScriptBin "run-openocd-block" ''
-		openocd -f board/st_nucleo_h743zi.cfg
+		openocd -f openocd/openocd.cfg
 	'';

 	setGDBConfigFile = writeShellScriptBin "set-gdb-config-file" ''
--- a/src/attenuator.rs
+++ b/src/attenuator.rs
@ -1,5 +1,4 @@
 use embedded_hal::blocking::spi::Transfer;
-use cortex_m_semihosting::hprintln;
 use core::assert;

 use crate::Error;
--- a/src/config_register.rs
+++ b/src/config_register.rs
@ -1,5 +1,4 @@
 use embedded_hal::blocking::spi::Transfer;
-use cortex_m_semihosting::hprintln;
 use crate::Error;
 use core::mem::size_of;

--- a/src/dds.rs
+++ b/src/dds.rs
@ -1,5 +1,4 @@
 use embedded_hal::blocking::spi::Transfer;
-use cortex_m_semihosting::hprintln;
 use crate::Error;
 use core::mem::size_of;

--- a/src/lib.rs
+++ b/src/lib.rs
@ -10,7 +10,6 @@ use core::{
 	marker::PhantomData,
 };
 use cortex_m;
-use cortex_m_semihosting::hprintln;

 #[macro_use]
 pub mod bitmask_macro;
--- a/src/nal_tcp_client.rs
+++ b/src/nal_tcp_client.rs
@ -6,8 +6,6 @@ use heapless::{consts, Vec};
 use stm32h7xx_hal::ethernet;
 use smoltcp as net;

-use cortex_m_semihosting::hprintln;
-
 use minimq::embedded_nal;

 #[derive(Debug)]
@ -61,7 +59,6 @@ impl<'a, 'b, 'c, 'n> NetworkStack<'a, 'b, 'c, 'n> {
        ) {
            Ok(changed) => changed == false,
            Err(e) => {
-                hprintln!("{:?}", e);
                true
            }
        }
--- a/src/scpi.rs
+++ b/src/scpi.rs
@ -31,7 +31,6 @@ use scpi::{
 // use scpi::suffix::{Frequency};

 use embedded_hal::blocking::spi::Transfer;
-use cortex_m_semihosting::hprintln;

 use crate::{
    Urukul,
@ -271,7 +270,6 @@ impl<T:Device + UrukulTraits> Command<T> for ClockDivisionCommand {
            Some(token) => {
                match f32::try_from(token) {
                    Ok(val) => {
-                        hprintln!("{}", val).unwrap();
                        if val == 1.0 || val == 2.0 || val == 4.0 {
                            val as u8
                        } else {
@ -279,7 +277,6 @@ impl<T:Device + UrukulTraits> Command<T> for ClockDivisionCommand {
                        }
                    },
                    Err(_e) => {
-                        hprintln!("Checked numberic error").unwrap();
                        return Err(ErrorCode::IllegalParameterValue.into())
                    },
                }
Author	SHA1	Message	Date
occheung	ecdb114679	src: replace hprint with logging	2020-09-10 14:35:47 +08:00
occheung	b954449ceb	eth ex: support tcp client	2020-09-10 14:35:11 +08:00
occheung	05b056d273	eth clock: init	2020-09-10 14:34:31 +08:00
occheung	1821b55fc1	cargo: cleanup dependencies	2020-09-10 10:29:35 +08:00
occheung	a45d5e5604	logger: init	2020-09-10 10:28:51 +08:00
occheung	c0084bc26d	openocd: init itm	2020-09-10 10:27:52 +08:00
occheung	cd9767efc0	gitignore: add itm.fifo	2020-09-10 10:26:22 +08:00