dds: add register io

.cargo/config

@@ -1,5 +1,5 @@
 [target.thumbv7em-none-eabihf]
-runner = "gdb -q -x gdb_config/openocd.gdb"
+runner = "gdb -q -x gdb_config/fpga_config.gdb"
 rustflags = [
   "-C", "link-arg=-Tlink.x",
 ]

src/bitmask_macro.rs

@@ -1,3 +1,5 @@
+use core::mem::size_of;
+
 /*
  * Macro builder for bit masks
  * $collection: Name for the bit mask collection
@@ -8,7 +10,7 @@
 
 macro_rules! construct_bitmask {
 	($collection: ident; $unsigned_type: ty; $($name: ident, $shift: expr, $width: expr),+) => {
-		#[derive(Debug, Copy, Clone)]
+		#[derive(Debug, Copy, Clone, PartialEq, Eq)]
 		pub enum $collection {
 			$(
 				$name,
@@ -33,13 +35,13 @@ macro_rules! construct_bitmask {
 			pub(crate) fn get_bitmask(self) -> $unsigned_type {
 				let mut mask: $unsigned_type = 0;
 				for bit in 0..self.get_width() {
-					mask |= (1 << (self.get_shift() + bit));
+					mask |= (1 << (self.get_shift() + bit) % ((size_of::<$unsigned_type>() as u8) * 8));
 				}
 				mask
 			}
 			pub(crate) fn get_shifted_bits(self, arg: $unsigned_type) -> $unsigned_type {
 				assert!(arg < (2 << self.get_width()));
-				(arg << self.get_shift())
+				(arg << (self.get_shift() % ((size_of::<$unsigned_type>() as u8) * 8)))
 			}
 			pub(crate) fn set_data_by_arg(self, data: &mut $unsigned_type, arg: $unsigned_type) {
 				// Clear bits in field, then insert shifted argument
@@ -48,7 +50,7 @@ macro_rules! construct_bitmask {
 			}
 			pub(crate) fn get_filtered_content(self, data: $unsigned_type) -> $unsigned_type {
 				// Filter everything then shift bits
-				((data & self.get_bitmask()) >> self.get_shift())
+				((data & self.get_bitmask()) >> (self.get_shift() % ((size_of::<$unsigned_type>() as u8) * 8)))
 			}
 		}
 	}

src/config_register.rs

@@ -1,6 +1,7 @@
 use embedded_hal::blocking::spi::Transfer;
 use cortex_m_semihosting::hprintln;
 use crate::Error;
+use core::mem::size_of;
 
 // Bitmasks for CFG
 construct_bitmask!(CFGMask; u32;
@@ -81,7 +82,7 @@ where
 	}
 
 	/*
-	 * Return status
+	 * Return status using mask
 	 */
 	pub fn get_status(&mut self, status_type: StatusMask) -> Result<u8, Error<E>> {
 		match self.set_all_configurations() {
@@ -89,6 +90,14 @@ where
 			Err(e) => Err(e),
 		}
 	}
+
+	/*
+	 * Return entire status register
+	 */
+	pub fn get_all_status(&mut self) -> Result<u32, Error<E>> {
+		return self.set_all_configurations();
+	}
+	
 }
 
 impl<SPI, E> Transfer<u8> for ConfigRegister<SPI>

src/dds.rs

@@ -1,8 +1,13 @@
 use embedded_hal::blocking::spi::Transfer;
 use cortex_m_semihosting::hprintln;
 use crate::Error;
+use core::mem::size_of;
 
-construct_bitmask!(CFR1Mask; u32;
+/*
+ *  Bitmask for all configurations (Order: CFR3, CFR2, CFR1)
+ */
+construct_bitmask!(DDSCFRMask; u32;
+	// CFR1 bitmasks
 	LSB_FIRST,						0,	1,
 	SDIO_IN_ONLY,					1,	1,
 	EXT_POWER_DOWN_CTRL,			3,	1,
@@ -23,38 +28,36 @@ construct_bitmask!(CFR1Mask; u32;
 	INV_SINC_FILTER_ENABLE,			22,	1,
 	MANUAL_OSK_EXT_CTRL,			23,	1,
 	RAM_PLAYBACK_DST,				29,	2,
-	RAM_ENABLE,						31,	1
+	RAM_ENABLE,						31,	1,
-);
 
-construct_bitmask!(CFR2Mask; u32;
+	// CFR2 bitmasks
-	FM_GAIN,						0,	4,
+	FM_GAIN,						0  +32,	4,
-	PARALLEL_DATA_PORT_ENABLE,		4,	1,
+	PARALLEL_DATA_PORT_ENABLE,		4  +32,	1,
-	SYNC_TIM_VALIDATION_DISABLE,	5,	1,
+	SYNC_TIM_VALIDATION_DISABLE,	5  +32,	1,
-	DATA_ASSEM_HOLD_LAST_VALUE,		6,	1,
+	DATA_ASSEM_HOLD_LAST_VALUE,		6  +32,	1,
-	MATCHED_LATENCY_ENABLE,			7,	1,
+	MATCHED_LATENCY_ENABLE,			7  +32,	1,
-	TXENABLE_INV,					9,	1,
+	TXENABLE_INV,					9  +32,	1,
-	PDCLK_INV,						10,	1,
+	PDCLK_INV,						10 +32,	1,
-	PDCLK_ENABLE,					11,	1,
+	PDCLK_ENABLE,					11 +32,	1,
-	IO_UPDATE_RATE_CTRL,			14,	2,
+	IO_UPDATE_RATE_CTRL,			14 +32,	2,
-	READ_EFFECTIVE_FTW,				16,	1,
+	READ_EFFECTIVE_FTW,				16 +32,	1,
-	DIGITAL_RAMP_NO_DWELL_LOW,		17,	1,
+	DIGITAL_RAMP_NO_DWELL_LOW,		17 +32,	1,
-	DIGITAL_RAMP_NO_DWELL_HIGH,		18,	1,
+	DIGITAL_RAMP_NO_DWELL_HIGH,		18 +32,	1,
-	DIGITAL_RAMP_ENABLE,			19,	1,
+	DIGITAL_RAMP_ENABLE,			19 +32,	1,
-	DIGITAL_RAMP_DEST,				20,	2,
+	DIGITAL_RAMP_DEST,				20 +32,	2,
-	SYNC_CLK_ENABLE,				22,	1,	
+	SYNC_CLK_ENABLE,				22 +32,	1,	
-	INT_IO_UPDATE_ACTIVE,			23,	1,
+	INT_IO_UPDATE_ACTIVE,			23 +32,	1,
-	EN_AMP_SCALE_SINGLE_TONE_PRO,	24,	1
+	EN_AMP_SCALE_SINGLE_TONE_PRO,	24 +32,	1,
-);
 
-construct_bitmask!(CFR3Mask; u32;
+	// CFR3 bitmasks
-	N,								1,	7,
+	N,								1  +64,	7,
-	PLL_ENABLE,						8,	1,
+	PLL_ENABLE,						8  +64,	1,
-	PFD_RESET,						10,	1,
+	PFD_RESET,						10 +64,	1,
-	REFCLK_IN_DIV_RESETB,			14,	1,
+	REFCLK_IN_DIV_RESETB,			14 +64,	1,
-	REFCLK_IN_DIV_BYPASS,			15,	1,
+	REFCLK_IN_DIV_BYPASS,			15 +64,	1,
-	I_CP,							19,	3,
+	I_CP,							19 +64,	3,
-	VCO_SEL,						24,	3,
+	VCO_SEL,						24 +64,	3,
-	DRV0,							28,	2
+	DRV0,							28 +64,	2
 );
 
 const WRITE_MASK 	:u8 = 0x00;
@@ -86,6 +89,100 @@ where
 	}
 }
 
+/*
+ *  Implement init
+ */
+ impl<SPI, E> DDS<SPI>
+ where
+	SPI: Transfer<u8, Error = E>
+ {
+	pub fn init(&mut self) -> Result<(), Error<E>> {
+		match self.write_register(0x00, &mut [
+			0x00, 0x00, 0x00, 0x02
+		]) {
+			Ok(_) => Ok(()),
+			Err(e) => Err(e),
+		}
+	}
+ }
+
+/*
+ *  Impleement configurations registers I/O through bitmasks
+ */
+impl<SPI, E> DDS<SPI>
+where
+	SPI: Transfer<u8, Error = E>
+{
+	/*
+	 *  Return (cfr1, cfr2, cfr3) contents
+	 */
+	fn get_all_configurations(&mut self) -> Result<[u32; 3], Error<E>> {
+		let mut cfr_reg = [0; 12];
+		self.read_register(0x00, &mut cfr_reg[0..4])?;
+		self.read_register(0x01, &mut cfr_reg[4..8])?;
+		self.read_register(0x02, &mut cfr_reg[8..12])?;
+		Ok([
+			(cfr_reg[0] as u32) << 24 | (cfr_reg[1] as u32) << 16 | (cfr_reg[2] as u32) << 8 | (cfr_reg[3] as u32),
+			(cfr_reg[4] as u32) << 24 | (cfr_reg[5] as u32) << 16 | (cfr_reg[6] as u32) << 8 | (cfr_reg[7] as u32),
+			(cfr_reg[8] as u32) << 24 | (cfr_reg[9] as u32) << 16 | (cfr_reg[10] as u32) << 8 | (cfr_reg[11] as u32)
+		])
+	}
+
+	/*
+	 *  Get a set of configurations using DDSCFRMask
+	 */
+	pub fn get_configurations<'w>(&mut self, mask_pairs: &'w mut[(DDSCFRMask, u32)]) -> Result<&'w [(DDSCFRMask, u32)], Error<E>> {
+		let data_array = self.get_all_configurations()?;
+		for index in 0..mask_pairs.len() {
+			mask_pairs[index].1 = match mask_pairs[index].0.get_shift() {
+				0..=31 => mask_pairs[index].0.get_filtered_content(data_array[0]),
+				32..=63 => mask_pairs[index].0.get_filtered_content(data_array[1]),
+				64..=95 => mask_pairs[index].0.get_filtered_content(data_array[2]),
+				_ => panic!("Invalid DDSCFRMask!"),
+			}
+		}
+		Ok(mask_pairs)
+	}
+
+	/*
+	 *  Write (cfr1, cfr2, cfr3) contents
+	 */
+	fn set_all_configurations(&mut self, data_array: [u32; 3]) -> Result<(), Error<E>> {
+		for register in 0x00..=0x02 {
+			self.write_register(register, &mut [
+				((data_array[register as usize] >> 24) & 0xFF) as u8,
+				((data_array[register as usize] >> 16) & 0xFF) as u8,
+				((data_array[register as usize] >> 8 ) & 0xFF) as u8,
+				((data_array[register as usize] >> 0 ) & 0xFF) as u8
+			])?;
+		}
+		Ok(())
+	}
+
+	/*
+	 *  Set a set of configurations using DDSCFRMask
+	 */
+	pub fn set_configurations(&mut self, mask_pairs: &mut[(DDSCFRMask, u32)]) -> Result<(), Error<E>> {
+		let mut data_array = self.get_all_configurations()?;
+		hprintln!("Initial array {:#X?}", data_array).unwrap();
+		for index in 0..mask_pairs.len() {
+			// Reject any attempt to write LSB_FIRST and SBIO_INPUT_ONLY
+			if mask_pairs[index].0 == DDSCFRMask::LSB_FIRST || mask_pairs[index].0 == DDSCFRMask::SDIO_IN_ONLY {
+				continue;
+			}
+			match mask_pairs[index].0.get_shift() {
+				0..=31 => mask_pairs[index].0.set_data_by_arg(&mut data_array[0], mask_pairs[index].1),
+				32..=63 => mask_pairs[index].0.set_data_by_arg(&mut data_array[1], mask_pairs[index].1),
+				64..=95 => mask_pairs[index].0.set_data_by_arg(&mut data_array[2], mask_pairs[index].1),
+				_ => panic!("Invalid DDSCFRMask!"),
+			};
+		}
+		hprintln!("Modified array {:#X?}", data_array).unwrap();
+		self.set_all_configurations(data_array.clone())
+	}
+
+}
+
 macro_rules! impl_register_io {
 	($($reg_addr: expr, $reg_byte_size: expr),+) => {
 		impl<SPI, E> DDS<SPI>

src/lib.rs

@@ -6,6 +6,7 @@ use embedded_hal::{
 };
 
 use core::cell;
+use core::mem::size_of;
 
 use cortex_m;
 use cortex_m::asm::nop;
@@ -31,6 +32,7 @@ pub enum Error<E> {
 	GetRefMutDataError,
 	AttenuatorError,
 	IOUpdateError,
+	DDSError,
 }
 
 /*
@@ -63,7 +65,6 @@ where
 {
 	type Error = Error<E>;
 	fn select_chip(&mut self, chip: u8) -> Result<(), Self::Error> {
-		hprintln!("Selected chip {}.", chip);
 		match chip & (1 << 0) {
 			0 => self.chip_select.0.set_low(),
 			_ => self.chip_select.0.set_high(),

src/main.rs

@@ -26,7 +26,10 @@ use firmware::{
 		CFGMask,
 		StatusMask,
 	},
-	dds::DDS,
+	dds::{
+		DDS,
+		DDSCFRMask,
+	},
 };
 
 #[entry]
@@ -94,7 +97,7 @@ fn main() -> ! {
 		&ccdr.clocks,
 	);
 
-	let mut switch = CPLD::new(spi, (cs0, cs1, cs2), io_update);
+	let switch = CPLD::new(spi, (cs0, cs1, cs2), io_update);
 	let parts = switch.split();
 
 	let mut config = ConfigRegister::new(parts.spi1);
@@ -111,35 +114,63 @@ fn main() -> ! {
 	config.set_configurations(&mut [
 		(CFGMask::IO_RST, 0),
 		(CFGMask::RST, 0),
-		(CFGMask::RF_SW, 1)
+		(CFGMask::RF_SW, 13),
+		(CFGMask::DIV, 2)
 	]).unwrap();
 
-	dds0.write_register(0x00, &mut[
+	// dds0.write_register(0x00, &mut[
-		0x00, 0x00, 0x00, 0x02
+	// 	0x00, 0x00, 0x00, 0x02
+	// ]).unwrap();
+
+	// dds0.write_register(0x01, &mut[
+	// 	0x01, 0x01, 0x00, 0x20
+	// ]).unwrap();
+
+	// dds0.write_register(0x02, &mut[
+	// 	0x05, 0x38, 0xC5, 0x28
+	// ]).unwrap();
+
+	dds0.init().unwrap();
+
+	dds0.set_configurations(&mut [
+		(DDSCFRMask::PDCLK_ENABLE,					0),
+		(DDSCFRMask::READ_EFFECTIVE_FTW,			1),
+		(DDSCFRMask::DIGITAL_RAMP_ENABLE,			0),
+		(DDSCFRMask::EN_AMP_SCALE_SINGLE_TONE_PRO,	1),
+		(DDSCFRMask::N,								0x14),
+		(DDSCFRMask::PLL_ENABLE,					1),
+		(DDSCFRMask::PFD_RESET,						1),
+		(DDSCFRMask::REFCLK_IN_DIV_BYPASS,			1),
+		(DDSCFRMask::I_CP,							7),
+		(DDSCFRMask::VCO_SEL,						5),
+		(DDSCFRMask::DRV0,							0),
 	]).unwrap();
 
-	dds0.write_register(0x02, &mut[
+	hprintln!("{:#X?}", dds0.read_register(0x02, &mut[
-		0x01F, 0x3F, 0x41, 0x00
+		0x00, 0x00, 0x00, 0x00
+	]).unwrap()).unwrap();
+
+	dds0.set_configurations(&mut [
+		(DDSCFRMask::PFD_RESET,						0),
 	]).unwrap();
 
-	hprintln!("{:#X?}", dds0.read_register(0x00, &mut[
+	hprintln!("{:#X?}", dds0.read_register(0x02, &mut[
 		0x00, 0x00, 0x00, 0x00
 	]).unwrap()).unwrap();
 
 	// Calculate FTW
-	let f_out = 10_000_000;
+	let f_out = 8_008_135;
-	let f_sclk = 100_000_000;
+	let f_sclk = 100_000_000 / 2 * 20;
 	let resolution :u64 = 1 << 32;
 	let ftw = (resolution * f_out / f_sclk) as u32;
 
-	hprintln!("{}", ftw);
-
 	// Read single-tone profile 0
 	let mut profile :[u8; 8] = [0; 8];
 	dds0.read_register(0x0E, &mut profile).unwrap();
 
-	// Overwrite FTW on profile
+	// Overwrite FTW on profile 0
-	profile[0] = 0x20;
+	profile[0] = 0x1F;
+	profile[1] = 0xFF;
 	profile[4] = ((ftw >> 24) & 0xFF) as u8;
 	profile[5] = ((ftw >> 16) & 0xFF) as u8;
 	profile[6] = ((ftw >> 8 ) & 0xFF) as u8;
@@ -147,28 +178,22 @@ fn main() -> ! {
 
 	dds0.write_register(0x0E, &mut profile).unwrap();
 
-	hprintln!("{:#X?}", dds0.read_register(0x0E, &mut profile).unwrap()).unwrap();
-
 	// Attenuator
 	att.set_attenuation([
 		0.0, 31.5, 24.0, 0.0
 	]).unwrap();
 
-	hprintln!("{:#X?}", att.get_attenuation().unwrap()).unwrap();
+	hprintln!("{:#X?}", dds0.get_configurations(&mut
+		[
+			(DDSCFRMask::SDIO_IN_ONLY,					0),
+			(DDSCFRMask::LSB_FIRST,						0),
+			(DDSCFRMask::PROFILE_CTRL,					0),
+			(DDSCFRMask::EN_AMP_SCALE_SINGLE_TONE_PRO,	0),
+			(DDSCFRMask::DRV0,							0),
+			(DDSCFRMask::VCO_SEL,						0)
+		]
+	).unwrap()).unwrap();
 
-/*
-	// Write to FTW register
-	dds0.write_register(0x07, &mut [
-		((ftw >> 24) & 0xFF) as u8,
-		((ftw >> 16) & 0xFF) as u8,
-		((ftw >> 8 ) & 0xFF) as u8,
-		((ftw >> 0 ) & 0xFF) as u8,
-	]).unwrap();
-
-	hprintln!("{:#X?}", dds0.read_register(0x07, &mut [
-		0x00, 0x00, 0x00, 0x00
-	]).unwrap()).unwrap();
-*/	
 	loop {}
 }