scpi: implement rst
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d78f85721f
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@ -131,7 +131,7 @@ fn main() -> ! {
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.sys_ck(200.mhz())
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.hclk(200.mhz())
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.pll1_r_ck(100.mhz()) // for TRACECK
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.pll1_q_ck(48.mhz())
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.pll1_q_ck(48.mhz()) // for SPI
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.freeze(vos, &dp.SYSCFG);
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// Get the delay provider.
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116
src/dds.rs
116
src/dds.rs
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@ -144,33 +144,36 @@ where
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let divider = f_sys_clk / self.f_ref_clk;
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// Reject extreme divider values. However, accept no frequency division
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if ((divider > 127 || divider < 12) && divider != 1) {
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panic!("Invalid divider value for PLL!");
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// panic!("Invalid divider value for PLL!");
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return Err(Error::DDSCLKError);
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}
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// Select a VCO
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let vco = if divider == 1 {
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6 // Bypass PLL if no frequency division needed
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} else if f_sys_clk > 1_150_000_000 {
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panic!("Invalid divider value for PLL!")
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} else if f_sys_clk > 820_000_000 {
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5
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} else if f_sys_clk > 700_000_000 {
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4
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} else if f_sys_clk > 600_000_000 {
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3
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} else if f_sys_clk > 500_000_000 {
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2
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} else if f_sys_clk > 420_000_000 {
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1
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} else if f_sys_clk > 370_000_000 {
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0
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} else {
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7 // Bypass PLL if f_sys_clk is too low
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};
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// // Select a VCO
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// let vco = if divider == 1 {
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// 6 // Bypass PLL if no frequency division needed
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// } else if f_sys_clk > 1_150_000_000 {
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// panic!("Invalid divider value for PLL!")
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// } else if f_sys_clk > 820_000_000 {
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// 5
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// } else if f_sys_clk > 700_000_000 {
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// 4
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// } else if f_sys_clk > 600_000_000 {
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// 3
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// } else if f_sys_clk > 500_000_000 {
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// 2
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// } else if f_sys_clk > 420_000_000 {
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// 1
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// } else if f_sys_clk > 370_000_000 {
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// 0
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// } else {
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// 7 // Bypass PLL if f_sys_clk is too low
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// };
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let vco = self.get_VCO_no(f_sys_clk, divider as u8)?;
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self.set_configurations(&mut [
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// Enable PLL, set divider (valid or not) and VCO
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(DDSCFRMask::PLL_ENABLE, 1),
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(DDSCFRMask::N, divider as u32),
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(DDSCFRMask::VCO_SEL, vco),
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(DDSCFRMask::VCO_SEL, vco.into()),
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// Reset PLL lock before re-enabling it
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(DDSCFRMask::PFD_RESET, 1),
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])?;
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@ -182,9 +185,76 @@ where
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}
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// Change external clock source (ref_clk)
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pub fn set_ref_clk_frequency(&mut self, f_ref_clk: u64) {
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pub fn set_ref_clk_frequency(&mut self, f_ref_clk: u64) -> Result<(), Error<E>> {
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self.f_ref_clk = f_ref_clk;
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// TODO: Examine clock tree and update f_sys_clk
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let mut configuration_queries = [
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// Acquire PLL status
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(DDSCFRMask::PLL_ENABLE, 0),
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// Acquire N-divider, to adjust VCO if necessary
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(DDSCFRMask::N, 0),
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// Acquire REF_CLK divider bypass
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(DDSCFRMask::REFCLK_IN_DIV_BYPASS, 0)
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];
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self.get_configurations(&mut configuration_queries)?;
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if configuration_queries[0].1 == 1 {
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// Recalculate sys_clk
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let divider :u64 = configuration_queries[1].1.into();
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let f_sys_clk = self.f_ref_clk * divider;
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// Adjust VCO
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match self.get_VCO_no(f_sys_clk, divider as u8) {
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Ok(vco_no) => {
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self.set_configurations(&mut [
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// Update VCO selection
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(DDSCFRMask::VCO_SEL, vco_no.into()),
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// Reset PLL lock before re-enabling it
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(DDSCFRMask::PFD_RESET, 1),
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])?;
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self.set_configurations(&mut [
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(DDSCFRMask::PFD_RESET, 0),
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])?;
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// Update f_sys_clk from recalculation
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self.f_sys_clk = f_sys_clk;
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Ok(())
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},
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Err(_) => {
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// Forcibly turn off PLL, enable default clk tree (divide by 2)
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self.enable_divided_ref_clk()
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}
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}
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}
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else if configuration_queries[2].1 == 0 {
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self.f_sys_clk = self.f_ref_clk / 2;
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Ok(())
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}
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else {
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self.f_sys_clk = self.f_ref_clk;
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Ok(())
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}
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}
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fn get_VCO_no(&mut self, f_sys_clk: u64, divider: u8) -> Result<u8, Error<E>> {
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// Select a VCO
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if divider == 1 {
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Ok(6) // Bypass PLL if no frequency division needed
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} else if f_sys_clk > 1_150_000_000 {
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Err(Error::DDSCLKError)
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} else if f_sys_clk > 820_000_000 {
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Ok(5)
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} else if f_sys_clk > 700_000_000 {
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Ok(4)
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} else if f_sys_clk > 600_000_000 {
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Ok(3)
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} else if f_sys_clk > 500_000_000 {
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Ok(2)
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} else if f_sys_clk > 420_000_000 {
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Ok(1)
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} else if f_sys_clk > 370_000_000 {
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Ok(0)
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} else {
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Ok(7) // Bypass PLL if f_sys_clk is too low
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}
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}
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/*
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43
src/lib.rs
43
src/lib.rs
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@ -26,6 +26,7 @@ use crate::cpld::DoOnGetRefMutData;
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pub mod config_register;
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use crate::config_register::ConfigRegister;
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use crate::config_register::CFGMask;
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pub mod attenuator;
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use crate::attenuator::Attenuator;
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@ -46,6 +47,8 @@ pub enum Error<E> {
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AttenuatorError,
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IOUpdateError,
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DDSError,
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ConfigRegisterError,
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DDSCLKError,
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}
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/*
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@ -78,6 +81,46 @@ where
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],
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}
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}
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/*
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* Reset method. To be invoked by initialization and manual reset.
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* Only Urukul struct provides reset method.
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* DDS reset is controlled by Urukul (RST).
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* Attenuators only have shift register reset, which does not affect its data
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* CPLD only has a "all-zero" default state.
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*/
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pub fn reset(&mut self) -> Result<(), Error<E>> {
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// Reset DDS and attenuators
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self.config_register.set_configurations(&mut [
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(CFGMask::RST, 1),
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(CFGMask::IO_RST, 1),
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(CFGMask::IO_UPDATE, 0)
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])?;
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// Set 0 to all fields on configuration register.
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self.config_register.set_configurations(&mut [
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(CFGMask::RF_SW, 0),
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(CFGMask::LED, 0),
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(CFGMask::PROFILE, 0),
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(CFGMask::IO_UPDATE, 0),
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(CFGMask::MASK_NU, 0),
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(CFGMask::CLK_SEL0, 0),
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(CFGMask::SYNC_SEL, 0),
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(CFGMask::RST, 0),
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(CFGMask::IO_RST, 0),
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(CFGMask::CLK_SEL1, 0),
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(CFGMask::DIV, 0),
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])?;
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// Init all DDS chips. Configure SDIO as input only.
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for chip_no in 0..4 {
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self.dds[chip_no].init()?;
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}
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// Clock tree reset. CPLD divides clock frequency by 4 by default.
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for chip_no in 0..4 {
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self.dds[chip_no].set_ref_clk_frequency(25_000_000);
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}
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Ok(())
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}
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}
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// /*
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14
src/scpi.rs
14
src/scpi.rs
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@ -28,6 +28,8 @@ use scpi::{
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scpi_tree,
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};
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use embedded_hal::blocking::spi::Transfer;
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use crate::Urukul;
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// pub struct MyDevice;
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@ -50,13 +52,21 @@ impl Command for HelloWorldCommand {
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* Implement "Device" trait from SCPI
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* TODO: Implement mandatory commands
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*/
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impl<SPI> Device for Urukul<SPI> {
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impl<SPI, E> Device for Urukul<SPI>
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where
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SPI: Transfer<u8, Error = E>
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{
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fn cls(&mut self) -> Result<()> {
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Ok(())
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}
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fn rst(&mut self) -> Result<()> {
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Ok(())
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match self.reset() {
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Ok(_) => Ok(()),
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Err(_) => Err(Error::new(
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ErrorCode::HardwareError
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))
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}
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}
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}
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