dds: add cfg1 enum
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@ -85,7 +85,7 @@ where
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*/
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*/
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pub fn get_status(&mut self, status_type: StatusMask) -> Result<u8, Error<E>> {
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pub fn get_status(&mut self, status_type: StatusMask) -> Result<u8, Error<E>> {
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match self.set_all_configurations() {
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match self.set_all_configurations() {
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Ok(val) => Ok(((val & status_type.get_bitmask()) >> status_type.get_shift()) as u8),
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Ok(val) => Ok(status_type.get_filtered_content(val) as u8),
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Err(e) => Err(e),
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Err(e) => Err(e),
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}
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}
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}
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}
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24
src/dds.rs
24
src/dds.rs
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@ -2,6 +2,30 @@ use embedded_hal::blocking::spi::Transfer;
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use cortex_m_semihosting::hprintln;
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use cortex_m_semihosting::hprintln;
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use crate::Error;
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use crate::Error;
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construct_bitmask!(CFR1Mask; u32;
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LSB_FIRST, 0, 1,
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SDIO_IN_ONLY, 1, 1,
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EXT_POWER_DOWN_CTRL, 3, 1,
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AUX_DAC_POWER_DOWN, 4, 1,
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REFCLK_IN_POWER_DOWN, 5, 1,
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DAC_POWER_DOWN, 6, 1,
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DIGITAL_POWER_DOWN, 7, 1,
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SEL_AUTO_OSK, 8, 1,
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OSK_ENABLE, 9, 1,
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LOAD_ARR_IO_UPDATE, 10, 1,
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CLEAR_PHASE_ACU, 11, 1,
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CLEAR_DIGITAL_RAMP_ACU, 12, 1,
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AUTOCLEAR_PHASE_ACU, 13, 1,
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AUTOCLEAR_DIGITAL_RAMP_ACU, 14, 1,
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LOAD_LRR_IO_UPDATE, 15, 1,
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SEL_DDS_SIN_OUT, 16, 1,
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PROFILE_CTRL, 17, 4,
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INV_SINC_FILTER_ENABLE, 22, 1,
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MANUAL_OSK_EXT_CTRL, 23, 1,
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RAM_PLAYBACK_DST, 29, 2,
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RAM_ENABLE, 31, 1
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);
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pub struct DDS<SPI> {
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pub struct DDS<SPI> {
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spi: SPI,
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spi: SPI,
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}
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}
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