cfg_reg: init

src/attenuator.rs

@@ -1,7 +1,7 @@
 use embedded_hal::blocking::spi::Transfer;
 use cortex_m::asm::nop;
 use cortex_m_semihosting::hprintln;
-//use core::clone;
+use core::assert;
 
 use crate::Error;
 
@@ -34,14 +34,36 @@ where
 			self.data[i] = self.data[i] << 2;
 		}
 		let mut clone = self.data.clone();
-		hprintln!("Before Attenuation: {:?}", clone).unwrap();
 		match self.spi.transfer(&mut clone).map_err(Error::SPI) {
 			Ok(arr) => {
-				hprintln!("Attenuation array: {:?}", arr).unwrap()
+				Ok(self.data.clone())
 			},
-			err => nop()
-		};
-		Ok(clone.clone())
+			err => Err(Error::AttenuatorError)
+		}
+	}
+
+	pub fn set_channel_attenuation(&mut self, channel: u8, attenuation: f32) -> Result<u8, Error<E>> {
+		assert!((channel < 4) && (channel >= 0));
+		let mut arr: [f32; 4] = self.get_attenuation();
+		arr[channel as usize] = attenuation;
+		match self.set_attenuation(arr) {
+			Ok(v) => Ok(v[channel as usize]),
+			Err(e) => Err(e)
+		}
+	}
+
+	pub fn get_channel_attenuation(&mut self, channel: u8) -> f32 {
+		assert!((channel < 4) && (channel >= 0));
+		(self.data[channel as usize] as f32)/8.0
+	}
+
+	pub fn get_attenuation(&mut self) -> [f32; 4] {
+		[
+			self.get_channel_attenuation(0),
+			self.get_channel_attenuation(1),
+			self.get_channel_attenuation(2),
+			self.get_channel_attenuation(3),
+		]
 	}
 }
 

src/config_register.rs

@@ -0,0 +1,29 @@
+use embedded_hal::blocking::spi::Transfer
+
+/*
+ * Bit Masks for CFG_Write
+ */
+const RF_SW			:u32	= 0x0000000F;
+const LED			:u32	= 0x000000F0;
+const PROFILE		:u32	= 0x00000700;
+const IO_UPDATE		:u32	= 0x00001000;
+const MASK_NU		:u32	= 0x0001E000;
+const CLK_SEL0		:u32	= 0x00020000;
+const SYNC_SEL		:u32	= 0x00040000;
+const RST			:u32	= 0x00080000;
+const IO_RST		:u32	= 0x00100000;
+const CLK_SEL1		:u32	= 0x00200000;
+const DIV			:u32	= 0x00C00000;
+
+/*
+ * Bit Masks for CFG_Read
+ */
+const SMP_ERR		:u32	= 0x000000F0;
+const PLL_LOCK		:u32	= 0x00000F00;
+const IFC_MODE		:u32	= 0x0000F000;
+const PROTO_DEV		:u32	= 0x007F0000;
+
+pub struct ConfigRegister<SPI> {
+	spi: SPI,
+	data: u32,
+}

src/lib.rs

@@ -14,7 +14,7 @@ use cortex_m_semihosting::hprintln;
 pub mod spi_slave;
 use crate::spi_slave::Parts;
 
-pub mod generic_spi_device;
+//pub mod generic_spi_device;
 
 pub mod attenuator;
 
@@ -26,6 +26,7 @@ pub enum Error<E> {
 	SPI(E),
 	CSError,
 	GetRefMutDataError,
+	AttenuatorError,
 }
 
 /*

src/main.rs

@@ -20,7 +20,6 @@ use nb::block;
 use firmware;
 use firmware::{
 	CPLD,
-	generic_spi_device::SPIStub,
 	attenuator::Attenuator,
 };
 
@@ -86,12 +85,10 @@ fn main() -> ! {
 
 	let parts = switch.split();
 
-	let mut spi_stub = SPIStub::new(parts.spi1);
-	spi_stub.do_something();
-
 	let mut attenuator = Attenuator::new(parts.spi2);
 	let mut attenuation :[f32; 4] = [24.0, -5.0, 32.0, 10.2];
 	attenuator.set_attenuation(attenuation);
+	attenuator.set_channel_attenuation(2, 15.3);
 
 	loop {
 		nop();

src/spi_slave.rs

@@ -25,7 +25,6 @@ pub struct Parts<'a, DEV: 'a, SPI, CS0, CS1, CS2> {
 impl<'a, DEV, SPI, CS0, CS1, CS2> Parts<'a, DEV, SPI, CS0, CS1, CS2> {
 	pub(crate) fn new(cpld: &'a DEV) -> Self {
 		Parts {
-//			spi0: SPISlave(&cpld, 0, PhantomData),
 			spi1: SPISlave(&cpld, 1, PhantomData),
 			spi2: SPISlave(&cpld, 2, PhantomData),
 			spi3: SPISlave(&cpld, 3, PhantomData),
@@ -48,9 +47,9 @@ where
 	type Error = Error<E>;
 
 	fn transfer<'w>(&mut self, words: &'w mut[u8]) -> Result<&'w [u8], Self::Error> {
-		self.0.do_on_get_ref_mut_data(|mut dev| {
-			dev.select_chip(self.1)
-		})?;
-		self.0.do_on_get_ref_mut_data(move |mut dev| dev.spi.transfer(words).map_err(Error::SPI))		
+		self.0.do_on_get_ref_mut_data(move |mut dev| {
+			dev.select_chip(self.1);
+			dev.spi.transfer(words).map_err(Error::SPI)
+		})	
 	}
 }