scpi: implement tst
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f60ec09b29
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8dbf621679
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@ -78,6 +78,45 @@ where
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Err(e) => Err(e),
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}
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}
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/*
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* Test method for Attenuators.
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* Return the number of test failed.
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*/
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pub fn test(&mut self) -> Result<u32, Error<E>> {
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// Test attenuators by getting back the attenuation
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let mut error_count = 0;
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// Convert cached SPI data into attenuation floats
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let att_floats :[f32; 4] = [
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((self.data[3] ^ 0xFC) as f32) / 8.0,
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((self.data[2] ^ 0xFC) as f32) / 8.0,
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((self.data[1] ^ 0xFC) as f32) / 8.0,
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((self.data[0] ^ 0xFC) as f32) / 8.0,
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];
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// Set the attenuation to an arbitrary value, then read the attenuation
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self.set_attenuation([
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3.5, 9.5, 20.0, 28.5
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])?;
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match self.get_attenuation() {
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Ok(arr) => {
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if arr[0] != 3.5 {
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error_count += 1;
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}
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if arr[1] != 9.5 {
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error_count += 1;
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}
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if arr[2] != 20.0 {
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error_count += 1;
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}
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if arr[3] != 28.5 {
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error_count += 1;
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}
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},
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Err(_) => return Err(Error::AttenuatorError),
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};
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self.set_attenuation(att_floats)?;
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Ok(error_count)
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}
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}
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impl<SPI, E> Transfer<u8> for Attenuator<SPI>
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@ -97,7 +97,19 @@ where
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pub fn get_all_status(&mut self) -> Result<u32, Error<E>> {
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return self.set_all_configurations();
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}
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/*
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* Test method for Configuration Register.
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* Return the number of test failed.
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*/
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pub fn test(&mut self) -> Result<u32, Error<E>> {
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// Test configuration register by getting PROTO_KEY.
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match self.get_status(StatusMask::PROTO_KEY) {
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Ok(8) => Ok(0),
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Ok(_) => Ok(1),
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Err(_) => Err(Error::ConfigRegisterError),
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}
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}
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}
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impl<SPI, E> Transfer<u8> for ConfigRegister<SPI>
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44
src/dds.rs
44
src/dds.rs
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@ -147,26 +147,6 @@ where
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// panic!("Invalid divider value for PLL!");
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return Err(Error::DDSCLKError);
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}
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// // Select a VCO
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// let vco = if divider == 1 {
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// 6 // Bypass PLL if no frequency division needed
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// } else if f_sys_clk > 1_150_000_000 {
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// panic!("Invalid divider value for PLL!")
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// } else if f_sys_clk > 820_000_000 {
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// 5
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// } else if f_sys_clk > 700_000_000 {
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// 4
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// } else if f_sys_clk > 600_000_000 {
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// 3
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// } else if f_sys_clk > 500_000_000 {
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// 2
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// } else if f_sys_clk > 420_000_000 {
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// 1
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// } else if f_sys_clk > 370_000_000 {
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// 0
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// } else {
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// 7 // Bypass PLL if f_sys_clk is too low
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// };
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let vco = self.get_VCO_no(f_sys_clk, divider as u8)?;
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self.set_configurations(&mut [
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@ -366,7 +346,29 @@ where
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((ftw >> 8 ) & 0xFF) as u8,
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((ftw >> 0 ) & 0xFF) as u8,
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])
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}
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}
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/*
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* Test method for DDS.
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* Return the number of test failed.
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*/
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pub fn test(&mut self) -> Result<u32, Error<E>> {
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// Test configuration register by getting SDIO_IN_ONLY and LSB_FIRST.
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let mut error_count = 0;
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let mut config_checks = [
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(DDSCFRMask::SDIO_IN_ONLY, 0),
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(DDSCFRMask::LSB_FIRST, 0)
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];
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self.get_configurations(&mut config_checks)?;
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if config_checks[0].1 == 0 {
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error_count += 1;
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}
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if config_checks[1].1 == 1 {
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error_count += 1;
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}
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Ok(error_count)
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}
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}
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16
src/lib.rs
16
src/lib.rs
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@ -27,6 +27,7 @@ use crate::cpld::DoOnGetRefMutData;
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pub mod config_register;
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use crate::config_register::ConfigRegister;
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use crate::config_register::CFGMask;
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use crate::config_register::StatusMask;
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pub mod attenuator;
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use crate::attenuator::Attenuator;
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@ -117,10 +118,23 @@ where
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// Clock tree reset. CPLD divides clock frequency by 4 by default.
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for chip_no in 0..4 {
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self.dds[chip_no].set_ref_clk_frequency(25_000_000);
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self.dds[chip_no].set_ref_clk_frequency(25_000_000)?;
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}
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Ok(())
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}
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/*
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* Test method fo Urukul.
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* Return the number of test failed.
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*/
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pub fn test(&mut self) -> Result<u32, Error<E>> {
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let mut count = self.config_register.test()?;
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count += self.attenuator.test()?;
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for chip_no in 0..4 {
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count += self.dds[chip_no].test()?;
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}
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Ok(count)
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}
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}
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// /*
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12
src/scpi.rs
12
src/scpi.rs
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@ -68,6 +68,18 @@ where
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))
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}
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}
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fn tst(&mut self) -> Result<()> {
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match self.test() {
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Ok(0) => Ok(()),
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Ok(_) => Err(Error::new(
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ErrorCode::SelfTestFailed
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)),
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Err(_) => Err(Error::new(
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ErrorCode::SelfTestFailed
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)),
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}
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}
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}
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pub const TREE: &Node = scpi_tree![
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