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migen: use extension

This commit is contained in:
occheung 2020-09-17 09:55:20 +08:00
parent 1be44e256d
commit 52b285742e
2 changed files with 28 additions and 62 deletions
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41
migen/fpga_config.py
View File

@ -1,4 +1,10 @@
from humpback import HumpbackPlatform # from humpback import HumpbackPlatform
# Import built in I/O, Connectors & Platform template
from migen.build.platforms.sinara import humpback
# Import migen platform for Lattice Products
from migen.build.lattice import LatticePlatform
# Import migen pin record structure
from migen.build.generic_platform import *
from migen.fhdl.module import Module from migen.fhdl.module import Module
from migen.fhdl.specials import Instance from migen.fhdl.specials import Instance
from migen.fhdl.bitcontainer import value_bits_sign from migen.fhdl.bitcontainer import value_bits_sign
@ -20,14 +26,15 @@ class UrukulConnector(Module):
platform.request("eem0", 6) platform.request("eem0", 6)
] ]
spi = platform.request("spi") spi = platform.request("spi")
spi_cs = platform.request("spi_cs")
led = platform.request("user_led") led = platform.request("user_led")
io_update = platform.request("io_update") io_update = platform.request("io_update")
# Assert SPI resource length assert len(spi.clk) == 1
assert len(spi.sclk) == 1
assert len(spi.mosi) == 1 assert len(spi.mosi) == 1
assert len(spi.miso) == 1 assert len(spi.miso) == 1
assert len(spi.cs) == 3 assert len(spi_cs) == 3
assert len(io_update) == 1
# TODO: Assert EEM resources # TODO: Assert EEM resources
assert isinstance(eem0, list) assert isinstance(eem0, list)
@ -46,22 +53,22 @@ class UrukulConnector(Module):
# Link EEM to SPI # Link EEM to SPI
self.comb += [ self.comb += [
eem0[0].p.eq(spi.sclk), eem0[0].p.eq(spi.clk),
eem0[0].n.eq(~spi.sclk), eem0[0].n.eq(~spi.clk),
eem0[1].p.eq(spi.mosi), eem0[1].p.eq(spi.mosi),
eem0[1].n.eq(~spi.mosi), eem0[1].n.eq(~spi.mosi),
spi.miso.eq(~self.miso_n), spi.miso.eq(~self.miso_n),
eem0[3].p.eq(spi.cs[0]), eem0[3].p.eq(spi_cs[0]),
eem0[3].n.eq(~spi.cs[0]), eem0[3].n.eq(~spi_cs[0]),
eem0[4].p.eq(spi.cs[1]), eem0[4].p.eq(spi_cs[1]),
eem0[4].n.eq(~spi.cs[1]), eem0[4].n.eq(~spi_cs[1]),
eem0[5].p.eq(spi.cs[2]), eem0[5].p.eq(spi_cs[2]),
eem0[5].n.eq(~spi.cs[2]), eem0[5].n.eq(~spi_cs[2]),
eem0[6].p.eq(io_update), eem0[6].p.eq(io_update),
eem0[6].n.eq(~io_update), eem0[6].n.eq(~io_update),
@ -71,5 +78,13 @@ class UrukulConnector(Module):
if __name__ == "__main__": if __name__ == "__main__":
platform = HumpbackPlatform() spi_cs = [
("spi_cs", 0, Pins("B13 B14 B15"), IOStandard("LVCMOS33"))
]
io_update = [
("io_update", 0, Pins("A11"), IOStandard("LVCMOS33"))
]
platform = humpback.Platform()
platform.add_extension(spi_cs)
platform.add_extension(io_update)
platform.build(UrukulConnector(platform)) platform.build(UrukulConnector(platform))

49
migen/humpback.py
View File

@ -1,49 +0,0 @@
# Import built in I/O, Connectors & Platform template
from migen.build.platforms.sinara.humpback import _io, _connectors, Platform
# Import migen platform for Lattice Products
from migen.build.lattice import LatticePlatform
# Import migen pin record structure
from migen.build.generic_platform import *
# Modify the SPI record, to include all 3 CS pins
'''
sclk -> PA5 : C8
mosi -> PB5 : N5
miso -> PA6 : T2
cs_0 -> PB12: B13
cs_1 -> PA15: B14
cs_2 -> PC7 : B15
'''
# Filter out SPI record
_io = [record for record in _io if record[0] != "spi"]
# Reinsert new SPI record, without MISO
_io.append(
("spi", 0,
Subsignal("cs" , Pins("B13 B14 B15")),
Subsignal("sclk", Pins("C8")),
Subsignal("mosi", Pins("N5")),
Subsignal("miso", Pins("T2")),
IOStandard("LVCMOS33"),
)
)
# Resource: DDS I/O_Update
'''
io_update -> PB15 : A11
'''
_io.append(
("io_update", 0, Pins("A11"), IOStandard("LVCMOS33"))
)
# Inherit Platform to gain the programmed clock attribute
class HumpbackPlatform(Platform):
def __init__(self):
LatticePlatform.__init__(self, "ice40-hx8k-ct256", _io, _connectors, toolchain="icestorm")
# Syntax check for direct execution
if __name__ == "__main__":
platform = HumpbackPlatform()