Bug fixes:
+ Manage I/O Update pulse width. - Remove retry-till-success PLL setup. * Filter away unused bit in ASF when reading from DDS * Reduce log from SPI
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@ -49,6 +49,11 @@ where
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pub(crate) fn issue_io_update(&mut self) -> Result<(), Error<E>> {
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pub(crate) fn issue_io_update(&mut self) -> Result<(), Error<E>> {
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self.io_update.set_high().map_err(|_| Error::IOUpdateError)?;
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self.io_update.set_high().map_err(|_| Error::IOUpdateError)?;
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// I/O Update minimum pulse width: 1 SYNC_CLK cycle
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// 1 SYNC_CLK cycle = 4 REF_CLK cycle, where f_ref_clk is at least 3.2 MHz
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// Therefore the maximum required pulse length is 1.25 us,
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// equivalent to 500 cycles with STM32 sysclk at 400 MHz, longer delay is provided.
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cortex_m::asm::delay(1_000);
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self.io_update.set_low().map_err(|_| Error::IOUpdateError)
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self.io_update.set_low().map_err(|_| Error::IOUpdateError)
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}
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}
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}
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}
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@ -411,7 +411,7 @@ where
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(profile_content[3] as u64);
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(profile_content[3] as u64);
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let phase: f64 = ((pow as f64)/(((1_u64) << 16) as f64))*360.0;
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let phase: f64 = ((pow as f64)/(((1_u64) << 16) as f64))*360.0;
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let asf: u64 = (profile_content[0] as u64) << 8 |
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let asf: u64 = ((profile_content[0] & 0x3F) as u64) << 8 |
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(profile_content[1] as u64);
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(profile_content[1] as u64);
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let amplitude: f64 = (asf as f64)/(((1_u64) << 14) as f64);
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let amplitude: f64 = (asf as f64)/(((1_u64) << 14) as f64);
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@ -64,7 +64,7 @@ use cortex_m_log::{
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lazy_static! {
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lazy_static! {
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static ref LOGGER: Logger<ItmSync<InterruptFree>> = Logger {
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static ref LOGGER: Logger<ItmSync<InterruptFree>> = Logger {
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level: LevelFilter::Trace,
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level: LevelFilter::Info,
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inner: unsafe {
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inner: unsafe {
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InterruptSync::new(
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InterruptSync::new(
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ItmDest::new(cortex_m::Peripherals::steal().ITM)
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ItmDest::new(cortex_m::Peripherals::steal().ITM)
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@ -340,18 +340,7 @@ where
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}
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}
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pub fn set_channel_sys_clk(&mut self, channel: u8, f_sys_clk: f64) -> Result<(), Error<E>> {
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pub fn set_channel_sys_clk(&mut self, channel: u8, f_sys_clk: f64) -> Result<(), Error<E>> {
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loop {
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self.dds[usize::from(channel)].set_sys_clk_frequency(f_sys_clk)
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if let Err(e) = self.dds[usize::from(channel)].set_sys_clk_frequency(f_sys_clk).map(|_| ()) {
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if e.is_wait_retry() {
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cortex_m::asm::delay(400_000);
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} else {
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return Err(e);
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}
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} else {
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break;
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}
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}
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Ok(())
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}
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}
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pub fn get_channel_sys_clk(&mut self, channel: u8) -> Result<f64, Error<E>> {
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pub fn get_channel_sys_clk(&mut self, channel: u8) -> Result<f64, Error<E>> {
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