dds: improve comment
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@ -187,6 +187,9 @@ where
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// Change external clock source (ref_clk)
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// Change external clock source (ref_clk)
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// This will always provide a legitimate f_sys_clk by the following priority
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// 1. Keep DDS clock tree untouched, record the new f_sys_clk
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// 2. Use the default divided-by-2 clock tree, if PLL configuration becomes invalid
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pub fn set_ref_clk_frequency(&mut self, f_ref_clk: f64) -> Result<(), Error<E>> {
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pub fn set_ref_clk_frequency(&mut self, f_ref_clk: f64) -> Result<(), Error<E>> {
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// Override old reference clock frequency (ref_clk)
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// Override old reference clock frequency (ref_clk)
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self.f_ref_clk = f_ref_clk;
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self.f_ref_clk = f_ref_clk;
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