dds: add ram control
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3edc4c6957
commit
3211261488
256
src/dds.rs
256
src/dds.rs
@ -2,7 +2,8 @@ use embedded_hal::blocking::spi::Transfer;
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use crate::Error;
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use core::mem::size_of;
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use core::convert::TryInto;
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use arrayvec::ArrayVec;
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use heapless::Vec;
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use heapless::consts::*;
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/*
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* Bitmask for all configurations (Order: CFR3, CFR2, CFR1)
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@ -64,6 +65,8 @@ construct_bitmask!(DDSCFRMask; u32;
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const WRITE_MASK :u8 = 0x00;
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const READ_MASK :u8 = 0x80;
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static mut RAM_VEC: Vec<u8, U8192> = Vec(heapless::i::Vec::new());
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#[derive(Clone, PartialEq)]
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pub enum RAMDestination {
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Frequency = 0,
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@ -483,94 +486,167 @@ where
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}
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/*
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* Configure a RAM mode profile, but with RAM data generated by a closure
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* Configure a RAM mode profile, wrt supplied frequency data
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* This will setup the static RAM_VEC by converting frequency to ftw
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*/
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pub fn set_ram_profile_with_closure<F>(&mut self, profile: u8, start_addr: u16,
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ram_dst: RAMDestination, no_dwell_high: bool, zero_crossing: bool,
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op_mode: RAMOperationMode, playback_rate: f64, f: F) -> Result<(), Error<E>>
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where
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F: FnOnce() -> ArrayVec::<[f64; 2048]>
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{
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// Check the legality of the profile setup
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assert!(profile < 7);
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assert!(start_addr < 1024);
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let mut vec = f();
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if (ram_dst != RAMDestination::Polar && ((vec.len() as u16) + start_addr) < 1024) ||
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((((vec.len()/2) as u16) + start_addr) < 1024) {
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return Err(Error::DDSRAMError);
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}
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// TODO: Convert argument into bytes for RAM
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let mut byte_vec: ArrayVec<[u8; 8192]> = ArrayVec::new();
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match ram_dst {
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RAMDestination::Frequency => {
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for freq in vec.into_iter() {
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let ftw = self.frequency_to_ftw(freq);
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byte_vec.push(((ftw >> 24) & 0xFF) as u8);
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byte_vec.push(((ftw >> 16) & 0xFF) as u8);
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byte_vec.push(((ftw >> 8) & 0xFF) as u8);
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byte_vec.push(((ftw >> 0) & 0xFF) as u8);
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}
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}
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RAMDestination::Phase => {
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for deg in vec.into_iter() {
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let pow = self.degree_to_pow(deg);
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byte_vec.push(((pow >> 8) & 0xFF) as u8);
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byte_vec.push(((pow >> 0) & 0xFF) as u8);
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byte_vec.push(0);
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byte_vec.push(0);
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}
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}
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RAMDestination::Amplitude => {
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for amp in vec.into_iter() {
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let asf = self.amplitude_to_asf(amp);
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byte_vec.push(((asf >> 8) & 0xFF) as u8);
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byte_vec.push(((asf << 2) & 0xFC) as u8);
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byte_vec.push(0);
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byte_vec.push(0);
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}
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}
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RAMDestination::Polar => {
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// Alternate phase and amplitude
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let mut phase = true;
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for pol in vec.into_iter() {
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if phase {
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let pow = self.degree_to_pow(pol);
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byte_vec.push(((pow >> 8) & 0xFF) as u8);
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byte_vec.push(((pow >> 0) & 0xFF) as u8);
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phase = false;
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} else {
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let asf = self.amplitude_to_asf(pol);
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byte_vec.push(((asf >> 8) & 0xFF) as u8);
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byte_vec.push(((asf << 2) & 0xFC) as u8);
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phase = true;
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}
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}
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if phase {
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return Err(Error::DDSRAMError);
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}
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}
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}
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let data = byte_vec.as_slice();
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self.set_ram_profile(profile, start_addr, start_addr + (((data.len()/4) - 1) as u16),
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ram_dst, no_dwell_high, zero_crossing, op_mode, playback_rate, data)
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}
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/*
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* Configure a RAM mode profile
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* TODO: Possibly remove redundant end_addr parameter.
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* This can be inferred by start_addr and data size.
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*/
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pub fn set_ram_profile(&mut self, profile: u8, start_addr: u16, end_addr: u16,
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ram_dst: RAMDestination, no_dwell_high: bool, zero_crossing: bool,
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op_mode: RAMOperationMode, playback_rate: f64, data: &[u8]
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pub unsafe fn set_frequency_ram_profile(&mut self, profile: u8, start_addr: u16, end_addr: u16,
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no_dwell_high: bool, zero_crossing: bool, op_mode: RAMOperationMode, playback_rate: f64,
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frequency_data: &[f64]
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) -> Result<(), Error<E>> {
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// Check the legality of the profile setup
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assert!(profile < 7);
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assert!(profile <= 7);
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assert!(end_addr >= start_addr);
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assert!(end_addr < 1024);
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assert_eq!(data.len() as u16, (end_addr - start_addr + 1) * 4);
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assert_eq!(frequency_data.len() as u16, end_addr - start_addr + 1);
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// Clear RAM vector, and add address byte
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RAM_VEC.clear();
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RAM_VEC.push(0x16)
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.map_err(|_| Error::DDSRAMError)?;
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// Convert frequency data into bytes recognized by DDS
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for freq in frequency_data.iter() {
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let ftw = self.frequency_to_ftw(*freq);
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RAM_VEC.push(((ftw >> 24) & 0xFF) as u8)
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.map_err(|_| Error::DDSRAMError)?;
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RAM_VEC.push(((ftw >> 16) & 0xFF) as u8)
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.map_err(|_| Error::DDSRAMError)?;
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RAM_VEC.push(((ftw >> 8) & 0xFF) as u8)
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.map_err(|_| Error::DDSRAMError)?;
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RAM_VEC.push(((ftw >> 0) & 0xFF) as u8)
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.map_err(|_| Error::DDSRAMError)?;
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}
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self.set_ram_profile(profile, start_addr, end_addr, RAMDestination::Frequency,
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no_dwell_high, zero_crossing, op_mode, playback_rate)
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}
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/*
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* Configure a RAM mode profile, wrt supplied amplitude data
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* This will setup the static RAM_VEC by converting amplitude to asf
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*/
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pub unsafe fn set_amplitude_ram_profile(&mut self, profile: u8, start_addr: u16, end_addr: u16,
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no_dwell_high: bool, zero_crossing: bool, op_mode: RAMOperationMode, playback_rate: f64,
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amplitude_data: &[f64]
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) -> Result<(), Error<E>> {
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// Check the legality of the profile setup
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assert!(profile <= 7);
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assert!(end_addr >= start_addr);
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assert!(end_addr < 1024);
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assert_eq!(amplitude_data.len() as u16, end_addr - start_addr + 1);
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// Clear RAM vector, and add address byte
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RAM_VEC.clear();
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RAM_VEC.push(0x16)
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.map_err(|_| Error::DDSRAMError)?;
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// Convert amplitude data into bytes recognized by DDS
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for amp in amplitude_data.iter() {
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let asf = self.amplitude_to_asf(*amp);
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RAM_VEC.push(((asf >> 8) & 0xFF) as u8)
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.map_err(|_| Error::DDSRAMError)?;
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RAM_VEC.push(((asf << 2) & 0xFC) as u8)
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.map_err(|_| Error::DDSRAMError)?;
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RAM_VEC.push(0)
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.map_err(|_| Error::DDSRAMError)?;
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RAM_VEC.push(0)
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.map_err(|_| Error::DDSRAMError)?;
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}
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self.set_ram_profile(profile, start_addr, end_addr, RAMDestination::Amplitude,
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no_dwell_high, zero_crossing, op_mode, playback_rate)
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}
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/*
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* Configure a RAM mode profile, wrt supplied phase data
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* This will setup the static RAM_VEC by converting phase to ftw
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*/
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pub unsafe fn set_phase_ram_profile(&mut self, profile: u8, start_addr: u16, end_addr: u16,
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no_dwell_high: bool, zero_crossing: bool, op_mode: RAMOperationMode, playback_rate: f64,
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phase_data: &[f64]
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) -> Result<(), Error<E>> {
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// Check the legality of the profile setup
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assert!(profile <= 7);
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assert!(end_addr >= start_addr);
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assert!(end_addr < 1024);
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assert_eq!(phase_data.len() as u16, end_addr - start_addr + 1);
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// Clear RAM vector, and add address byte
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RAM_VEC.clear();
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RAM_VEC.push(0x16)
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.map_err(|_| Error::DDSRAMError)?;
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// Convert phase data into bytes recognized by DDS
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for deg in phase_data.iter() {
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let pow = self.degree_to_pow(*deg);
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RAM_VEC.push(((pow >> 8) & 0xFF) as u8)
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.map_err(|_| Error::DDSRAMError)?;
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RAM_VEC.push(((pow >> 0) & 0xFF) as u8)
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.map_err(|_| Error::DDSRAMError)?;
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RAM_VEC.push(0)
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.map_err(|_| Error::DDSRAMError)?;
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RAM_VEC.push(0)
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.map_err(|_| Error::DDSRAMError)?;
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}
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self.set_ram_profile(profile, start_addr, end_addr, RAMDestination::Phase,
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no_dwell_high, zero_crossing, op_mode, playback_rate)
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}
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/*
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* Configure a RAM mode profile, wrt supplied phase data
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* This will setup the static RAM_VEC by converting phase to ftw
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*/
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pub unsafe fn set_polar_ram_profile(&mut self, profile: u8, start_addr: u16, end_addr: u16,
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no_dwell_high: bool, zero_crossing: bool, op_mode: RAMOperationMode, playback_rate: f64,
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polar_data: &[(f64, f64)]
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) -> Result<(), Error<E>> {
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// Check the legality of the profile setup
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assert!(profile <= 7);
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assert!(end_addr >= start_addr);
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assert!(end_addr < 1024);
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assert_eq!(polar_data.len() as u16, end_addr - start_addr + 1);
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// Clear RAM vector, and add address byte
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RAM_VEC.clear();
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RAM_VEC.push(0x16)
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.map_err(|_| Error::DDSRAMError)?;
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// Convert amplitude data into bytes recognized by DDS
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for (deg, amp) in polar_data.iter() {
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let pow = self.degree_to_pow(*deg);
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let asf = self.amplitude_to_asf(*amp);
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RAM_VEC.push(((pow >> 8) & 0xFF) as u8)
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.map_err(|_| Error::DDSRAMError)?;
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RAM_VEC.push(((pow >> 0) & 0xFF) as u8)
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.map_err(|_| Error::DDSRAMError)?;
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RAM_VEC.push(((asf >> 8) & 0xFF) as u8)
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.map_err(|_| Error::DDSRAMError)?;
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RAM_VEC.push(((asf << 2) & 0xFC) as u8)
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.map_err(|_| Error::DDSRAMError)?;
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}
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self.set_ram_profile(profile, start_addr, end_addr, RAMDestination::Phase,
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no_dwell_high, zero_crossing, op_mode, playback_rate)
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}
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/*
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* Configure a RAM mode profile, w.r.t static vector (RAM_VEC)
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*/
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fn set_ram_profile(&mut self, profile: u8, start_addr: u16, end_addr: u16,
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ram_dst: RAMDestination, no_dwell_high: bool, zero_crossing: bool,
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op_mode: RAMOperationMode, playback_rate: f64
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) -> Result<(), Error<E>> {
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// Check the legality of the profile setup
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assert!(profile <= 7);
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assert!(end_addr >= start_addr);
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assert!(end_addr < 1024);
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// assert_eq! RAM_VEC.len() as u16, ((end_addr - start_addr + 1) * 4) + 1);
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// Calculate address step rate, and check legality
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let step_rate = (self.f_sys_clk/(4.0 * playback_rate)) as u64;
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@ -595,7 +671,9 @@ where
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// Temporarily disable RAM mode while accessing into RAM
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self.disable_ram_configuration()?;
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self.write_ram(data)?;
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unsafe {
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self.write_ram()?;
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}
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// Properly configure start_addr and end_addr
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self.enable_ram_configuration(ram_dst)
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@ -622,14 +700,8 @@ where
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}
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// Write data in RAM
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fn write_ram(&mut self, data: &[u8]) -> Result<(), Error<E>> {
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let mut vec: ArrayVec<[u8; 8192]> = ArrayVec::new();
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vec.try_push(0x16)
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.map_err(|_| Error::DDSRAMError)?;
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vec.try_extend_from_slice(data)
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.map_err(|_| Error::DDSRAMError)?;
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let mut data_slice = vec.as_mut_slice();
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self.spi.transfer(&mut data_slice)
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unsafe fn write_ram(&mut self) -> Result<(), Error<E>> {
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self.spi.transfer(&mut RAM_VEC)
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.map(|_| ())
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.map_err(Error::SPI)
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}
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