urukul: add master clock div getter
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@ -75,7 +75,6 @@ where
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/*
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/*
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* Return selected configuration field
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* Return selected configuration field
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* TODO: Return result type instead for error checking
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*/
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*/
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pub fn get_configuration(&mut self, config_type: CFGMask) -> u8 {
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pub fn get_configuration(&mut self, config_type: CFGMask) -> u8 {
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config_type.get_filtered_content(self.data) as u8
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config_type.get_filtered_content(self.data) as u8
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11
src/lib.rs
11
src/lib.rs
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@ -231,7 +231,7 @@ where
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fn set_dds_ref_clk(&mut self) -> Result<(), Error<E>> {
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fn set_dds_ref_clk(&mut self) -> Result<(), Error<E>> {
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// Calculate reference clock frequency after clock division from configuration register
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// Calculate reference clock frequency after clock division from configuration register
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let f_ref_clk = self.f_master_clk / (self.config_register.get_configuration(CFGMask::DIV) as f64);
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let f_ref_clk = self.f_master_clk / (self.get_master_clock_division() as f64);
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// Update all DDS chips on reference clock frequency
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// Update all DDS chips on reference clock frequency
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for dds_channel in 0..4 {
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for dds_channel in 0..4 {
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@ -240,6 +240,15 @@ where
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Ok(())
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Ok(())
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}
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}
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fn get_master_clock_division(&mut self) -> u8 {
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match self.config_register.get_configuration(CFGMask::DIV) {
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0 | 3 => 4,
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1 => 1,
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2 => 2,
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_ => panic!("Divisor out of range, when reading configuration register (CPLD)."),
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}
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}
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fn set_channel_attenuation(&mut self, channel: u8, attenuation: f32) -> Result<(), Error<E>> {
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fn set_channel_attenuation(&mut self, channel: u8, attenuation: f32) -> Result<(), Error<E>> {
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if channel >= 4 || attenuation < 0.0 || attenuation > 31.5 {
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if channel >= 4 || attenuation < 0.0 || attenuation > 31.5 {
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return Err(Error::ParameterError);
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return Err(Error::ParameterError);
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