dds: add RAM mode
This commit is contained in:
parent
a5dbfdaf4f
commit
25f8363e54
13
Cargo.toml
13
Cargo.toml
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@ -13,7 +13,6 @@ embedded-hal = "0.2.4"
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stm32h7xx-hal = {version = "0.7.1", features = [ "stm32h743v", "rt", "unproven", "ethernet", "phy_lan8742a" ] }
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stm32h7xx-hal = {version = "0.7.1", features = [ "stm32h743v", "rt", "unproven", "ethernet", "phy_lan8742a" ] }
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smoltcp = { version = "0.6.0", default-features = false, features = [ "ethernet", "proto-ipv4", "proto-ipv6", "socket-tcp", "log" ] }
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smoltcp = { version = "0.6.0", default-features = false, features = [ "ethernet", "proto-ipv4", "proto-ipv6", "socket-tcp", "log" ] }
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nb = "1.0.0"
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nb = "1.0.0"
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libm = "0.2.0"
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embedded-nal = "0.1.0"
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embedded-nal = "0.1.0"
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minimq = { git = "https://github.com/quartiq/minimq.git", branch = "master" }
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minimq = { git = "https://github.com/quartiq/minimq.git", branch = "master" }
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@ -33,6 +32,18 @@ branch = "issue-4"
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default-features = false
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default-features = false
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features = [ "build-info", "unit-frequency", "unit-angle" ]
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features = [ "build-info", "unit-frequency", "unit-angle" ]
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# [dependencies.uom]
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# version = "0.29.0"
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# default-features = false
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# features = [
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# "autoconvert",
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# "usize", "u8", "u16", "u32", "u64",
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# "isize", "i8", "i16", "i32", "i64",
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# "f32", "f64",
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# "si",
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# "try-from"
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# ]
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# Use below SCPI dependency when need to modify SCPI fork offline
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# Use below SCPI dependency when need to modify SCPI fork offline
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# [dependencies.scpi]
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# [dependencies.scpi]
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# path = "../scpi-fork/scpi"
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# path = "../scpi-fork/scpi"
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158
src/dds.rs
158
src/dds.rs
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@ -1,7 +1,8 @@
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use embedded_hal::blocking::spi::Transfer;
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use embedded_hal::blocking::spi::Transfer;
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use crate::Error;
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use crate::Error;
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use core::mem::size_of;
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use core::mem::size_of;
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use libm::round;
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use core::convert::TryInto;
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use arrayvec::ArrayVec;
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/*
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/*
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* Bitmask for all configurations (Order: CFR3, CFR2, CFR1)
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* Bitmask for all configurations (Order: CFR3, CFR2, CFR1)
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@ -63,6 +64,23 @@ construct_bitmask!(DDSCFRMask; u32;
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const WRITE_MASK :u8 = 0x00;
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const WRITE_MASK :u8 = 0x00;
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const READ_MASK :u8 = 0x80;
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const READ_MASK :u8 = 0x80;
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#[derive(Clone)]
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pub enum RAMDestination {
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Frequency = 0,
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Phase = 1,
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Amplitude = 2,
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Polar = 3,
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}
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#[derive(Clone)]
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pub enum RAMOperationMode {
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DirectSwitch = 0,
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RampUp = 1,
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BidirectionalRamp = 2,
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ContinuousBidirectionalRamp = 3,
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ContinuousRecirculate = 4,
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}
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pub struct DDS<SPI> {
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pub struct DDS<SPI> {
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spi: SPI,
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spi: SPI,
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f_ref_clk: f64,
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f_ref_clk: f64,
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@ -143,7 +161,7 @@ where
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// Get a divider
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// Get a divider
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let divider = (f_sys_clk / self.f_ref_clk) as u64;
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let divider = (f_sys_clk / self.f_ref_clk) as u64;
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// Reject extreme divider values. However, accept no frequency division
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// Reject extreme divider values. However, accept no frequency division
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if ((divider > 127 || divider < 12) && divider != 1) {
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if (divider > 127 || divider < 12) && divider != 1 {
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// panic!("Invalid divider value for PLL!");
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// panic!("Invalid divider value for PLL!");
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return Err(Error::DDSCLKError);
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return Err(Error::DDSCLKError);
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}
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}
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@ -345,16 +363,10 @@ where
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} else {
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} else {
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((resolutions[2] as f64) * amp_scale_factor) as u16
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((resolutions[2] as f64) * amp_scale_factor) as u16
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};
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};
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// Setup configuration registers before writing single tone register
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// Setup configuration registers before writing single tone register
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self.set_configurations(&mut [
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self.enable_single_tone_configuration()?;
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(DDSCFRMask::RAM_ENABLE, 0),
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(DDSCFRMask::DIGITAL_RAMP_ENABLE, 0),
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(DDSCFRMask::OSK_ENABLE, 0),
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(DDSCFRMask::PARALLEL_DATA_PORT_ENABLE, 0),
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])?;
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self.set_configurations(&mut [
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(DDSCFRMask::EN_AMP_SCALE_SINGLE_TONE_PRO, 1),
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])?;
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// Transfer single tone profile data
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// Transfer single tone profile data
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self.write_register(0x0E + profile, &mut [
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self.write_register(0x0E + profile, &mut [
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((asf >> 8 ) & 0xFF) as u8,
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((asf >> 8 ) & 0xFF) as u8,
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@ -376,15 +388,7 @@ where
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pub fn set_single_tone_profile_frequency(&mut self, profile: u8, f_out: f64) -> Result<(), Error<E>> {
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pub fn set_single_tone_profile_frequency(&mut self, profile: u8, f_out: f64) -> Result<(), Error<E>> {
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// Setup configuration registers before writing single tone register
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// Setup configuration registers before writing single tone register
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self.set_configurations(&mut [
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self.enable_single_tone_configuration()?;
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(DDSCFRMask::RAM_ENABLE, 0),
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(DDSCFRMask::DIGITAL_RAMP_ENABLE, 0),
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(DDSCFRMask::OSK_ENABLE, 0),
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(DDSCFRMask::PARALLEL_DATA_PORT_ENABLE, 0),
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])?;
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self.set_configurations(&mut [
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(DDSCFRMask::EN_AMP_SCALE_SINGLE_TONE_PRO, 1),
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])?;
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// Calculate frequency tuning work (FTW)
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// Calculate frequency tuning work (FTW)
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let f_res: u64 = 1 << 32;
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let f_res: u64 = 1 << 32;
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@ -412,15 +416,7 @@ where
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pub fn set_single_tone_profile_phase(&mut self, profile: u8, phase_offset: f64) -> Result<(), Error<E>> {
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pub fn set_single_tone_profile_phase(&mut self, profile: u8, phase_offset: f64) -> Result<(), Error<E>> {
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// Setup configuration registers before writing single tone register
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// Setup configuration registers before writing single tone register
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self.set_configurations(&mut [
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self.enable_single_tone_configuration()?;
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(DDSCFRMask::RAM_ENABLE, 0),
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(DDSCFRMask::DIGITAL_RAMP_ENABLE, 0),
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(DDSCFRMask::OSK_ENABLE, 0),
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(DDSCFRMask::PARALLEL_DATA_PORT_ENABLE, 0),
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])?;
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self.set_configurations(&mut [
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(DDSCFRMask::EN_AMP_SCALE_SINGLE_TONE_PRO, 1),
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])?;
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// Calculate phase offset work (POW)
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// Calculate phase offset work (POW)
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let phase_res: u64 = 1 << 16;
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let phase_res: u64 = 1 << 16;
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@ -446,15 +442,7 @@ where
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pub fn set_single_tone_profile_amplitude(&mut self, profile: u8, amp_scale_factor: f64) -> Result<(), Error<E>> {
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pub fn set_single_tone_profile_amplitude(&mut self, profile: u8, amp_scale_factor: f64) -> Result<(), Error<E>> {
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// Setup configuration registers before writing single tone register
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// Setup configuration registers before writing single tone register
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self.set_configurations(&mut [
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self.enable_single_tone_configuration()?;
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(DDSCFRMask::RAM_ENABLE, 0),
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(DDSCFRMask::DIGITAL_RAMP_ENABLE, 0),
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(DDSCFRMask::OSK_ENABLE, 0),
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(DDSCFRMask::PARALLEL_DATA_PORT_ENABLE, 0),
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])?;
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self.set_configurations(&mut [
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(DDSCFRMask::EN_AMP_SCALE_SINGLE_TONE_PRO, 1),
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])?;
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// Calculate amplitude_scale_factor (ASF)
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// Calculate amplitude_scale_factor (ASF)
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let amp_res: u64 = 1 << 14;
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let amp_res: u64 = 1 << 14;
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@ -476,6 +464,96 @@ where
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self.write_register(0x0E + profile, &mut register)
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self.write_register(0x0E + profile, &mut register)
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}
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}
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// Helper function to switch into single tone mode
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// Need to setup configuration registers before writing single tone register
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fn enable_single_tone_configuration(&mut self) -> Result<(), Error<E>> {
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self.set_configurations(&mut [
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(DDSCFRMask::RAM_ENABLE, 0),
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(DDSCFRMask::DIGITAL_RAMP_ENABLE, 0),
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(DDSCFRMask::OSK_ENABLE, 0),
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(DDSCFRMask::PARALLEL_DATA_PORT_ENABLE, 0),
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])?;
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self.set_configurations(&mut [
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(DDSCFRMask::EN_AMP_SCALE_SINGLE_TONE_PRO, 1),
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])
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}
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// Helper function to switch into RAM mode
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// Need to setup configuration registers before writing into RAM profile register
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fn enable_ram_configuration(&mut self, ram_dst: RAMDestination) -> Result<(), Error<E>> {
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self.set_configurations(&mut [
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(DDSCFRMask::RAM_ENABLE, 1),
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(DDSCFRMask::RAM_PLAYBACK_DST, ram_dst as u32),
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])
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}
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// Helper function to switch out of RAM mode
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// Need to setup configuration registers before writing into RAM profile register
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fn disable_ram_configuration(&mut self) -> Result<(), Error<E>> {
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self.set_configurations(&mut [
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(DDSCFRMask::RAM_ENABLE, 0),
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])
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}
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/*
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* Configure a RAM mode profile
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*
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*/
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pub fn set_ram_profile(&mut self, profile: u8, start_addr: u16, end_addr: u16,
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ram_dst: RAMDestination, no_dwell_high: bool, zero_crossing: bool,
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op_mode: RAMOperationMode, playback_rate: f64, data: &[u8]
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) -> Result<(), Error<E>> {
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// Check the legality of this setup
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assert!(profile < 7);
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assert!(end_addr >= start_addr);
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assert!(end_addr < 1024);
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assert_eq!(data.len() as u16, (end_addr - start_addr + 1) * 4);
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// Calculate address step rate, and check legality
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let step_rate = (self.f_sys_clk/(4.0 * playback_rate)) as u64;
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if (step_rate == 0 || step_rate > 0xFFFF) {
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return Err(Error::ParameterError);
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}
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// Before setting up RAM, disable RAM_ENABLE
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self.enable_ram_configuration(ram_dst.clone())?;
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// Write a RAM profile, but include all data in RAM
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self.write_register(0x0E + profile, &mut [
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0x00,
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((step_rate >> 8) & 0xFF).try_into().unwrap(),
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((step_rate >> 0) & 0xFF).try_into().unwrap(),
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((end_addr >> 2) & 0xFF).try_into().unwrap(),
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((end_addr & 0x3) << 6).try_into().unwrap(),
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((start_addr >> 2) & 0xFF).try_into().unwrap(),
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((start_addr & 0x3) << 6).try_into().unwrap(),
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((no_dwell_high as u8) << 5) | ((zero_crossing as u8) << 3) | (op_mode as u8)
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])?;
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// Temporarily disable RAM mode while accessing into RAM
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self.disable_ram_configuration();
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self.write_ram(data)?;
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// Properly configure start_addr and end_addr
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self.enable_ram_configuration(ram_dst)
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}
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// Helper function to write data in RAM
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// Need address range for data size check
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fn write_ram(&mut self, data: &[u8]) -> Result<(), Error<E>> {
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let mut vec: ArrayVec<[u8; 8192]> = ArrayVec::new();
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vec.try_push(0x16)
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.map_err(|_| Error::DDSRAMError)?;
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vec.try_extend_from_slice(data)
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.map_err(|_| Error::DDSRAMError)?;
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let mut data_slice = vec.as_mut_slice();
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self.spi.transfer(&mut data_slice)
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.map(|_| ())
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.map_err(Error::SPI)
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}
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/*
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/*
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* Test method for DDS.
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* Test method for DDS.
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@ -497,9 +575,9 @@ where
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}
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}
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Ok(error_count)
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Ok(error_count)
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}
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}
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}
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}
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// Strong check for bytes passed to a register
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macro_rules! impl_register_io {
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macro_rules! impl_register_io {
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($($reg_addr: expr, $reg_byte_size: expr),+) => {
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($($reg_addr: expr, $reg_byte_size: expr),+) => {
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impl<SPI, E> DDS<SPI>
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impl<SPI, E> DDS<SPI>
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@ -572,6 +650,4 @@ impl_register_io!(
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0x13, 8,
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0x13, 8,
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0x14, 8,
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0x14, 8,
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0x15, 8
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0x15, 8
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// RAM works in other way
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// 0x16, 4
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);
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);
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64
src/lib.rs
64
src/lib.rs
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@ -1,29 +1,14 @@
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#![no_std]
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#![no_std]
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#![feature(generic_associated_types)]
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#![feature(str_strip)]
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#![feature(str_strip)]
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extern crate embedded_hal;
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extern crate embedded_hal;
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use embedded_hal::{
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use embedded_hal::{
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digital::v2::OutputPin,
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blocking::spi::Transfer,
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blocking::spi::Transfer,
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};
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};
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use core::{
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cell,
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marker::PhantomData,
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};
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use cortex_m;
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#[macro_use]
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#[macro_use]
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pub mod bitmask_macro;
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pub mod bitmask_macro;
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pub mod spi_slave;
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pub mod spi_slave;
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use crate::spi_slave::{
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Parts,
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SPISlave,
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};
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pub mod cpld;
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pub mod cpld;
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use crate::cpld::CPLD;
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use crate::cpld::DoOnGetRefMutData;
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pub mod config_register;
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pub mod config_register;
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use crate::config_register::ConfigRegister;
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use crate::config_register::ConfigRegister;
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@ -36,11 +21,12 @@ use crate::attenuator::Attenuator;
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pub mod dds;
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pub mod dds;
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use crate::dds::DDS;
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use crate::dds::DDS;
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pub mod scpi;
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// pub mod scpi;
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pub mod translation;
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pub mod translation;
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pub mod nal_tcp_client;
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pub mod nal_tcp_client;
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pub mod flash;
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pub mod mqtt_mux;
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/*
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/*
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* Enum for structuring error
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* Enum for structuring error
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@ -55,7 +41,9 @@ pub enum Error<E> {
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DDSError,
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DDSError,
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ConfigRegisterError,
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ConfigRegisterError,
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DDSCLKError,
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DDSCLKError,
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DDSRAMError,
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ParameterError,
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ParameterError,
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MqttCommandError,
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}
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}
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#[derive(Debug)]
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#[derive(Debug)]
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@ -156,28 +144,12 @@ where
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}
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}
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}
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}
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pub trait UrukulTraits {
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impl<SPI, E> Urukul<SPI>
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type Error;
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fn get_channel_switch_status(&mut self, channel: u32) -> Result<bool, Self::Error>;
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fn set_channel_switch(&mut self, channel: u32, status: bool) -> Result<(), Self::Error>;
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fn set_clock_source(&mut self, source: ClockSource, frequency: f64) -> Result<(), Self::Error>;
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fn set_clock_division(&mut self, division: u8) -> Result<(), Self::Error>;
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fn set_channel_attenuation(&mut self, channel: u8, attenuation: f32) -> Result<(), Self::Error>;
|
|
||||||
fn set_profile(&mut self, profile: u8) -> Result<(), Self::Error>;
|
|
||||||
fn set_channel_single_tone_profile(&mut self, channel: u8, profile: u8, frequency: f64, phase: f64, amplitude: f64) -> Result<(), Self::Error>;
|
|
||||||
fn set_channel_single_tone_profile_frequency(&mut self, channel: u8, profile: u8, frequency: f64)-> Result<(), Self::Error>;
|
|
||||||
fn set_channel_single_tone_profile_phase(&mut self, channel: u8, profile: u8, phase: f64)-> Result<(), Self::Error>;
|
|
||||||
fn set_channel_single_tone_profile_amplitude(&mut self, channel: u8, profile: u8, amplitude: f64)-> Result<(), Self::Error>;
|
|
||||||
fn set_channel_sys_clk(&mut self, channel: u8, sys_clk: f64) -> Result<(), Self::Error>;
|
|
||||||
}
|
|
||||||
|
|
||||||
impl<SPI, E> UrukulTraits for Urukul<SPI>
|
|
||||||
where
|
where
|
||||||
SPI: Transfer<u8, Error = E>
|
SPI: Transfer<u8, Error = E>
|
||||||
{
|
{
|
||||||
type Error = Error<E>;
|
|
||||||
|
|
||||||
fn get_channel_switch_status(&mut self, channel: u32) -> Result<bool, Self::Error> {
|
fn get_channel_switch_status(&mut self, channel: u32) -> Result<bool, Error<E>> {
|
||||||
if channel < 4 {
|
if channel < 4 {
|
||||||
self.config_register.get_status(StatusMask::RF_SW).map(|val| (val & (1 << channel)) != 0)
|
self.config_register.get_status(StatusMask::RF_SW).map(|val| (val & (1 << channel)) != 0)
|
||||||
} else {
|
} else {
|
||||||
|
@ -185,7 +157,7 @@ where
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
fn set_channel_switch(&mut self, channel: u32, status: bool) -> Result<(), Self::Error> {
|
fn set_channel_switch(&mut self, channel: u32, status: bool) -> Result<(), Error<E>> {
|
||||||
if channel < 4 {
|
if channel < 4 {
|
||||||
let prev = u32::from(self.config_register.get_status(StatusMask::RF_SW)?);
|
let prev = u32::from(self.config_register.get_status(StatusMask::RF_SW)?);
|
||||||
let next = {
|
let next = {
|
||||||
|
@ -203,7 +175,7 @@ where
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
fn set_clock_source(&mut self, source: ClockSource, frequency: f64) -> Result<(), Self::Error> {
|
fn set_clock_source(&mut self, source: ClockSource, frequency: f64) -> Result<(), Error<E>> {
|
||||||
// Change clock source through configuration register
|
// Change clock source through configuration register
|
||||||
match source {
|
match source {
|
||||||
ClockSource::OSC => self.config_register.set_configurations(&mut [
|
ClockSource::OSC => self.config_register.set_configurations(&mut [
|
||||||
|
@ -232,7 +204,7 @@ where
|
||||||
Ok(())
|
Ok(())
|
||||||
}
|
}
|
||||||
|
|
||||||
fn set_clock_division(&mut self, division: u8) -> Result<(), Self::Error> {
|
fn set_clock_division(&mut self, division: u8) -> Result<(), Error<E>> {
|
||||||
match division {
|
match division {
|
||||||
1 => self.config_register.set_configurations(&mut [
|
1 => self.config_register.set_configurations(&mut [
|
||||||
(CFGMask::DIV, 1),
|
(CFGMask::DIV, 1),
|
||||||
|
@ -256,33 +228,33 @@ where
|
||||||
Ok(())
|
Ok(())
|
||||||
}
|
}
|
||||||
|
|
||||||
fn set_channel_attenuation(&mut self, channel: u8, attenuation: f32) -> Result<(), Self::Error> {
|
fn set_channel_attenuation(&mut self, channel: u8, attenuation: f32) -> Result<(), Error<E>> {
|
||||||
self.attenuator.set_channel_attenuation(channel, attenuation)
|
self.attenuator.set_channel_attenuation(channel, attenuation)
|
||||||
}
|
}
|
||||||
|
|
||||||
fn set_profile(&mut self, profile: u8) -> Result<(), Self::Error> {
|
fn set_profile(&mut self, profile: u8) -> Result<(), Error<E>> {
|
||||||
self.config_register.set_configurations(&mut [
|
self.config_register.set_configurations(&mut [
|
||||||
(CFGMask::PROFILE, profile.into())
|
(CFGMask::PROFILE, profile.into())
|
||||||
]).map(|_| ())
|
]).map(|_| ())
|
||||||
}
|
}
|
||||||
|
|
||||||
fn set_channel_single_tone_profile(&mut self, channel: u8, profile: u8, frequency: f64, phase: f64, amplitude: f64) -> Result<(), Self::Error> {
|
fn set_channel_single_tone_profile(&mut self, channel: u8, profile: u8, frequency: f64, phase: f64, amplitude: f64) -> Result<(), Error<E>> {
|
||||||
self.dds[usize::from(channel)].set_single_tone_profile(profile, frequency, phase, amplitude)
|
self.dds[usize::from(channel)].set_single_tone_profile(profile, frequency, phase, amplitude)
|
||||||
}
|
}
|
||||||
|
|
||||||
fn set_channel_single_tone_profile_frequency(&mut self, channel: u8, profile: u8, frequency: f64)-> Result<(), Self::Error> {
|
fn set_channel_single_tone_profile_frequency(&mut self, channel: u8, profile: u8, frequency: f64)-> Result<(), Error<E>> {
|
||||||
self.dds[usize::from(channel)].set_single_tone_profile_frequency(profile, frequency)
|
self.dds[usize::from(channel)].set_single_tone_profile_frequency(profile, frequency)
|
||||||
}
|
}
|
||||||
|
|
||||||
fn set_channel_single_tone_profile_phase(&mut self, channel: u8, profile: u8, phase: f64)-> Result<(), Self::Error> {
|
fn set_channel_single_tone_profile_phase(&mut self, channel: u8, profile: u8, phase: f64)-> Result<(), Error<E>> {
|
||||||
self.dds[usize::from(channel)].set_single_tone_profile_phase(profile, phase)
|
self.dds[usize::from(channel)].set_single_tone_profile_phase(profile, phase)
|
||||||
}
|
}
|
||||||
|
|
||||||
fn set_channel_single_tone_profile_amplitude(&mut self, channel: u8, profile: u8, amplitude: f64)-> Result<(), Self::Error> {
|
fn set_channel_single_tone_profile_amplitude(&mut self, channel: u8, profile: u8, amplitude: f64)-> Result<(), Error<E>> {
|
||||||
self.dds[usize::from(channel)].set_single_tone_profile_amplitude(profile, amplitude)
|
self.dds[usize::from(channel)].set_single_tone_profile_amplitude(profile, amplitude)
|
||||||
}
|
}
|
||||||
|
|
||||||
fn set_channel_sys_clk(&mut self, channel: u8, f_sys_clk: f64) -> Result<(), Self::Error> {
|
fn set_channel_sys_clk(&mut self, channel: u8, f_sys_clk: f64) -> Result<(), Error<E>> {
|
||||||
self.dds[usize::from(channel)].set_sys_clk_frequency(f_sys_clk)
|
self.dds[usize::from(channel)].set_sys_clk_frequency(f_sys_clk)
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
Loading…
Reference in New Issue