2
0
mirror of https://github.com/m-labs/artiq.git synced 2025-02-11 10:03:19 +08:00
artiq/artiq/gateware/targets
Harry Ho f6d39fd6ba kc705: revive DRTIO master with updated syntax
* KC705 master variant now uses Si5324 as synthesiser.
* Multi-channel has not been implemented yet.
2021-01-20 15:05:31 +08:00
..
__init__.py package everything to rebuild core device binaries 2015-11-09 10:47:14 +08:00
kasli_generic.py Merge branch 'master' into phaser 2020-09-22 16:02:25 +00:00
kasli.py kasli2: work around vivado clock constraint problem 2020-10-08 16:31:39 +08:00
kc705_drtio_master.py kc705: revive DRTIO master with updated syntax 2021-01-20 15:05:31 +08:00
kc705_drtio_satellite.py kc705: revive DRTIO satellite with updated syntax, update GTX 2021-01-20 11:25:38 +08:00
kc705.py build_soc: rename identifier_str to gateware_identifier_str 2020-09-02 00:00:57 +08:00
metlino.py build_soc: rename identifier_str to gateware_identifier_str 2020-09-02 00:00:57 +08:00
sayma_amc.py sayma: add comments about CPLL line rate on KU GTH 2020-12-19 17:05:20 +08:00
sayma_rtm.py build_soc: rename identifier_str to gateware_identifier_str 2020-09-02 00:00:57 +08:00